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[Qemu-commits] [qemu/qemu] f9e2b9: linux-user: Emulate /proc/cpuinfo out
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] f9e2b9: linux-user: Emulate /proc/cpuinfo output for riscv |
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Date: |
Fri, 12 May 2023 10:30:06 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: f9e2b99a44183d1e9abb65354fa5beb2243fded4
https://github.com/qemu/qemu/commit/f9e2b99a44183d1e9abb65354fa5beb2243fded4
Author: Afonso Bordado <afonsobordado@gmail.com>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/syscall.c
M tests/tcg/riscv64/Makefile.target
A tests/tcg/riscv64/cpuinfo.c
Log Message:
-----------
linux-user: Emulate /proc/cpuinfo output for riscv
RISC-V does not expose all extensions via hwcaps, thus some userspace
applications may want to query these via /proc/cpuinfo.
Currently when querying this file the host's file is shown instead
which is slightly confusing. Emulate a basic /proc/cpuinfo file
with mmu info and an ISA string.
Signed-off-by: Afonso Bordado <afonsobordado@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <167873059442.9885.15152085316575248452-0@git.sr.ht>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: bf676057e13430bfbc64d485e6a21672bd8f8992
https://github.com/qemu/qemu/commit/bf676057e13430bfbc64d485e6a21672bd8f8992
Author: Thomas Weißschuh <thomas@t-8ch.de>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: report ENOTTY for unknown ioctls
The correct error number for unknown ioctls is ENOTTY.
ENOSYS would mean that the ioctl() syscall itself is not implemented,
which is very improbable and unexpected for userspace.
ENOTTY means "Inappropriate ioctl for device". This is what the kernel
returns on unknown ioctls, what qemu is trying to express and what
userspace is prepared to handle.
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230426070659.80649-1-thomas@t-8ch.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: e526f3bd12bd2a4ba9c0cdf2c384b7e32e364b19
https://github.com/qemu/qemu/commit/e526f3bd12bd2a4ba9c0cdf2c384b7e32e364b19
Author: Thomas Weißschuh <thomas@t-8ch.de>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: Add move_mount() syscall
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20230424153429.276788-1-thomas@t-8ch.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: d57f76ef25c735c4a3de0608116ccfa02f0a9cf5
https://github.com/qemu/qemu/commit/d57f76ef25c735c4a3de0608116ccfa02f0a9cf5
Author: Thomas Weißschuh <thomas@t-8ch.de>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: Add open_tree() syscall
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20230424153429.276788-2-thomas@t-8ch.de>
[lv: move declaration at the beginning of the block]
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: a171aa5cd4b434361984726c566f0568b0442a35
https://github.com/qemu/qemu/commit/a171aa5cd4b434361984726c566f0568b0442a35
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/main.c
Log Message:
-----------
linux-user/main: Use list_cpus() instead of cpu_list()
This way we can get rid of the if'deffery and the XXX comment
here (it's repeated in the list_cpus() function anyway).
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230424122126.236586-1-thuth@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 359fc089559fb1672cfa9af34b0807073fdcf07d
https://github.com/qemu/qemu/commit/359fc089559fb1672cfa9af34b0807073fdcf07d
Author: Thomas Weißschuh <thomas@t-8ch.de>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/qemu.h
Log Message:
-----------
linux-user: Add new flag VERIFY_NONE
This can be used to validate that an address range is mapped but without
being readable or writable.
It will be used by an updated implementation of mincore().
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20230422100314.1650-2-thomas@t-8ch.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 6a274e1ab93327cece6f770c54f817497eb0f52f
https://github.com/qemu/qemu/commit/6a274e1ab93327cece6f770c54f817497eb0f52f
Author: Thomas Weißschuh <thomas@t-8ch.de>
Date: 2023-05-01 (Mon, 01 May 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: Don't require PROT_READ for mincore
The kernel does not require PROT_READ for addresses passed to mincore.
For example the fincore(1) tool from util-linux uses PROT_NONE and
currently does not work under qemu-user.
Example (with fincore(1) from util-linux 2.38):
$ fincore /proc/self/exe
RES PAGES SIZE FILE
24K 6 22.1K /proc/self/exe
$ qemu-x86_64 /usr/bin/fincore /proc/self/exe
fincore: failed to do mincore: /proc/self/exe: Cannot allocate memory
With this patch:
$ ./build/qemu-x86_64 /usr/bin/fincore /proc/self/exe
RES PAGES SIZE FILE
24K 6 22.1K /proc/self/exe
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20230422100314.1650-3-thomas@t-8ch.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 249cfb3b5289b1e8d556c9d11f76419fc8f7ae64
https://github.com/qemu/qemu/commit/249cfb3b5289b1e8d556c9d11f76419fc8f7ae64
Author: Daniil Kovalev <dkovalev@compiler-toolchain-for.me>
Date: 2023-05-02 (Tue, 02 May 2023)
Changed paths:
M linux-user/mips/cpu_loop.c
Log Message:
-----------
linux-user: Fix mips fp64 executables loading
If a program requires fr1, we should set the FR bit of CP0 control status
register and add F64 hardware flag. The corresponding `else if` branch
statement is copied from the linux kernel sources (see `arch_check_elf` function
in linux/arch/mips/kernel/elf.c).
Signed-off-by: Daniil Kovalev <dkovalev@compiler-toolchain-for.me>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230404052153.16617-1-dkovalev@compiler-toolchain-for.me>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: 3e7f6c76d529dd4096d043cbd16593e40b469e70
https://github.com/qemu/qemu/commit/3e7f6c76d529dd4096d043cbd16593e40b469e70
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: fix getgroups/setgroups allocations
linux-user getgroups(), setgroups(), getgroups32() and setgroups32()
used alloca() to allocate grouplist arrays, with unchecked gidsetsize
coming from the "guest". With NGROUPS_MAX being 65536 (linux, and it
is common for an application to allocate NGROUPS_MAX for getgroups()),
this means a typical allocation is half the megabyte on the stack.
Which just overflows stack, which leads to immediate SIGSEGV in actual
system getgroups() implementation.
An example of such issue is aptitude, eg
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=811087#72
Cap gidsetsize to NGROUPS_MAX (return EINVAL if it is larger than that),
and use heap allocation for grouplist instead of alloca(). While at it,
fix coding style and make all 4 implementations identical.
Try to not impose random limits - for example, allow gidsetsize to be
negative for getgroups() - just do not allocate negative-sized grouplist
in this case but still do actual getgroups() call. But do not allow
negative gidsetsize for setgroups() since its argument is unsigned.
Capping by NGROUPS_MAX seems a bit arbitrary, - we can do more, it is
not an error if set size will be NGROUPS_MAX+1. But we should not allow
integer overflow for the array being allocated. Maybe it is enough to
just call g_try_new() and return ENOMEM if it fails.
Maybe there's also no need to convert setgroups() since this one is
usually smaller and known beforehand (KERN_NGROUPS_MAX is actually 63, -
this is apparently a kernel-imposed limit for runtime group set).
The patch fixes aptitude segfault mentioned above.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20230409105327.1273372-1-mjt@msgid.tls.msk.ru>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit: c460132251e85eed22f7be4c75f444ce2e246912
https://github.com/qemu/qemu/commit/c460132251e85eed22f7be4c75f444ce2e246912
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
R target/arm/arm_ldst.h
R target/arm/sve_ldst_internal.h
A target/arm/tcg/arm_ldst.h
A target/arm/tcg/sve_ldst_internal.h
A target/arm/tcg/translate-a32.h
R target/arm/translate-a32.h
Log Message:
-----------
target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/
These files got missed when populating tcg/.
Because they are included with "", no change to the users required.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230504110412.1892411-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 67ce09b5443caf310649b5b003efe5b0d69e81a1
https://github.com/qemu/qemu/commit/67ce09b5443caf310649b5b003efe5b0d69e81a1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
R target/arm/helper-a64.h
R target/arm/helper-mve.h
R target/arm/helper-sme.h
R target/arm/helper-sve.h
M target/arm/helper.h
A target/arm/tcg/helper-a64.h
A target/arm/tcg/helper-mve.h
A target/arm/tcg/helper-sme.h
A target/arm/tcg/helper-sve.h
Log Message:
-----------
target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/
While we cannot move the main "helper.h" out of target/arm/,
due to usage by generic code, we can move the sub-includes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230504110412.1892411-3-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 21a4ab8318ba6f049aac244e237cd1557586e216
https://github.com/qemu/qemu/commit/21a4ab8318ba6f049aac244e237cd1557586e216
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Don't allow stage 2 page table walks to downgrade to NS
Bit 63 in a Table descriptor is only the NSTable bit for stage 1
translations; in stage 2 it is RES0. We were incorrectly looking at
it all the time.
This causes problems if:
* the stage 2 table descriptor was incorrectly setting the RES0 bit
* we are doing a stage 2 translation in Secure address space for
a NonSecure stage 1 regime -- in this case we would incorrectly
do an immediate downgrade to NonSecure
A bug elsewhere in the code currently prevents us from getting
to the second situation, but when we fix that it will be possible.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230504135425.2748672-2-peter.maydell@linaro.org
Commit: fcc0b0418fff655f20fd0cf86a1bbdc41fd2e7c6
https://github.com/qemu/qemu/commit/fcc0b0418fff655f20fd0cf86a1bbdc41fd2e7c6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Fix handling of SW and NSW bits for stage 2 walks
We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW
configuration bits. These allow configuration of whether the stage 2
page table walks for Secure IPA and NonSecure IPA should do their
descriptor reads from Secure or NonSecure physical addresses. (This
is separate from how the translation table base address and other
parameters are set: an NS IPA always uses VTTBR_EL2 and VTCR_EL2
for its base address and walk parameters, regardless of the NSW bit,
and similarly for Secure.)
Provide a new function ptw_idx_for_stage_2() which returns the
MMU index to use for descriptor reads, and use it to set up
the .in_ptw_idx wherever we call get_phys_addr_lpae().
For a stage 2 walk, wherever we call get_phys_addr_lpae():
* .in_ptw_idx should be ptw_idx_for_stage_2() of the .in_mmu_idx
* .in_secure should be true if .in_mmu_idx is Stage2_S
This allows us to correct S1_ptw_translate() so that it consistently
always sets its (out_secure, out_phys) to the result it gets from the
S2 walk (either by calling get_phys_addr_lpae() or by TLB lookup).
This makes better conceptual sense because the S2 walk should return
us an (address space, address) tuple, not an address that we then
randomly assign to S or NS.
Our previous handling of SW and NSW was broken, so guest code
trying to use these bits to put the s2 page tables in the "other"
address space wouldn't work correctly.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230504135425.2748672-3-peter.maydell@linaro.org
Commit: 4f9786327458c0e50d8e99066d1603ebe0e345c0
https://github.com/qemu/qemu/commit/4f9786327458c0e50d8e99066d1603ebe0e345c0
Author: Akihiko Odaki <akihiko.odaki@gmail.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update Akihiko Odaki's email address
I am now employed by Daynix. Although my role as a reviewer of
macOS-related change is not very relevant to the employment, I decided
to use the company email address to avoid confusions from different
addresses.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20230506072333.32510-1-akihiko.odaki@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd22a0f520f471e3bd33bc19cf3b2fa772cdb2a8
https://github.com/qemu/qemu/commit/cd22a0f520f471e3bd33bc19cf3b2fa772cdb2a8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M ui/console.c
Log Message:
-----------
ui: Fix pixel colour channel order for PNG screenshots
When we take a PNG screenshot the ordering of the colour channels in
the data is not correct, resulting in the image having weird
colouring compared to the actual display. (Specifically, on a
little-endian host the blue and red channels are swapped; on
big-endian everything is wrong.)
This happens because the pixman idea of the pixel data and the libpng
idea differ. PIXMAN_a8r8g8b8 defines that pixels are 32-bit values,
with A in bits 24-31, R in bits 16-23, G in bits 8-15 and B in bits
0-7. This means that on little-endian systems the bytes in memory
are
B G R A
and on big-endian systems they are
A R G B
libpng, on the other hand, thinks of pixels as being a series of
values for each channel, so its format PNG_COLOR_TYPE_RGB_ALPHA
always wants bytes in the order
R G B A
This isn't the same as the pixman order for either big or little
endian hosts.
The alpha channel is also unnecessary bulk in the output PNG file,
because there is no alpha information in a screenshot.
To handle the endianness issue, we already define in ui/qemu-pixman.h
various PIXMAN_BE_* and PIXMAN_LE_* values that give consistent
byte-order pixel channel formats. So we can use PIXMAN_BE_r8g8b8 and
PNG_COLOR_TYPE_RGB, which both have an in-memory byte order of
R G B
and 3 bytes per pixel.
(PPM format screenshots get this right; they already use the
PIXMAN_BE_r8g8b8 format.)
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1622
Fixes: 9a0a119a382867 ("Added parameter to take screenshot with screendump as
PNG")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 20230502135548.2451309-1-peter.maydell@linaro.org
Commit: d6359e150dbdf84f67add786473fd277a9a442bb
https://github.com/qemu/qemu/commit/d6359e150dbdf84f67add786473fd277a9a442bb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M docs/system/devices/igb.rst
M docs/system/devices/ivshmem.rst
M docs/system/devices/net.rst
M docs/system/devices/usb.rst
M docs/system/keys.rst
M docs/system/linuxboot.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs: Remove unused weirdly-named cross-reference targets
In the doc sources, we have a few cross-reference targets with odd
names "pcsys_005fxyz". These are the legacy of the semi-automated
conversion of the old info docs to rST (the '005f' is because ASCII
0x5f is '_' and the old info link names had underscores in them).
Remove the targets which nothing links to, and rename the two targets
which are used to something a bit more descriptive.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230421163642.1151904-1-peter.maydell@linaro.org
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Commit: 9d8299bf93eb7c2ea5fd64716352b9454fa7fe8c
https://github.com/qemu/qemu/commit/9d8299bf93eb7c2ea5fd64716352b9454fa7fe8c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Fix minor dead code issue
Coverity points out (in CID 1508390) that write_bootloader has
some dead code, where we assign to 'p' and then in the following
line assign to it again. This happened as a result of the
refactoring in commit cd5066f8618b.
Fix the dead code by removing the 'void *v' variable entirely and
instead adding a cast when calling bl_setup_gt64120_jump_kernel(), as
we do at its other callsite in write_bootloader_nanomips().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f773a31ece66744705eda794752767df29f8c8d8
https://github.com/qemu/qemu/commit/f773a31ece66744705eda794752767df29f8c8d8
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/arm/Kconfig
Log Message:
-----------
target/arm: Select SEMIHOSTING when using TCG
Semihosting has been made a 'default y' entry in Kconfig, which does
not work because when building --without-default-devices, the
semihosting code would not be available.
Make semihosting unconditional when TCG is present.
Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only
build")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230508181611.2621-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a117e87212ca1da8221e4ccbdeed3bedba5dc8f3
https://github.com/qemu/qemu/commit/a117e87212ca1da8221e4ccbdeed3bedba5dc8f3
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/arm/Kconfig
Log Message:
-----------
target/arm: Select CONFIG_ARM_V7M when TCG is enabled
We cannot allow this config to be disabled at the moment as not all of
the relevant code is protected by it.
Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a
KVM-only build") moved the CONFIGs of several boards to Kconfig, so it
is now possible that nothing selects ARM_V7M (e.g. when doing a
--without-default-devices build).
Return the CONFIG_ARM_V7M entry to a state where it is always selected
whenever TCG is available.
Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only
build")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230508181611.2621-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c726fa701c14f088241e2f3f89b0c25ffabeac3c
https://github.com/qemu/qemu/commit/c726fa701c14f088241e2f3f89b0c25ffabeac3c
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/qtest/cdrom-test.c
Log Message:
-----------
tests/qtest: Don't run cdrom boot tests if no accelerator is present
On a build configured with: --disable-tcg --enable-xen it is possible
to produce a QEMU binary with no TCG nor KVM support. Skip the cdrom
boot tests if that's the case.
Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230508181611.2621-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 478dccbb99db0bf8f00537dd0b4d0de88d5cb537
https://github.com/qemu/qemu/commit/478dccbb99db0bf8f00537dd0b4d0de88d5cb537
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/pauth_helper.c
Log Message:
-----------
target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
In check_s2_mmu_setup() we have a check that is attempting to
implement the part of AArch64.S2MinTxSZ that is specific to when EL1
is AArch32:
if !s1aarch64 then
// EL1 is AArch32
min_txsz = Min(min_txsz, 24);
Unfortunately we got this wrong in two ways:
(1) The minimum txsz corresponds to a maximum inputsize, but we got
the sense of the comparison wrong and were faulting for all
inputsizes less than 40 bits
(2) We try to implement this as an extra check that happens after
we've done the same txsz checks we would do for an AArch64 EL1, but
in fact the pseudocode is *loosening* the requirements, so that txsz
values that would fault for an AArch64 EL1 do not fault for AArch32
EL1, because it does Min(old_min, 24), not Max(old_min, 24).
You can see this also in the text of the Arm ARM in table D8-8, which
shows that where the implemented PA size is less than 40 bits an
AArch32 EL1 is still OK with a configured stage2 T0SZ for a 40 bit
IPA, whereas if EL1 is AArch64 then the T0SZ must be big enough to
constrain the IPA to the implemented PA size.
Because of part (2), we can't do this as a separate check, but
have to integrate it into aa64_va_parameters(). Add a new argument
to that function to indicate that EL1 is 32-bit. All the existing
callsites except the one in get_phys_addr_lpae() can pass 'false',
because they are either doing a lookup for a stage 1 regime or
else they don't care about the tsz/tsz_oob fields.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1627
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230509092059.3176487-1-peter.maydell@linaro.org
Commit: 9e5ee2364e2a77a4938cd0f948585e5918147700
https://github.com/qemu/qemu/commit/9e5ee2364e2a77a4938cd0f948585e5918147700
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M linux-user/main.c
M linux-user/mips/cpu_loop.c
M linux-user/qemu.h
M linux-user/syscall.c
M tests/tcg/riscv64/Makefile.target
A tests/tcg/riscv64/cpuinfo.c
Log Message:
-----------
Merge tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu
into staging
linux-user pull request 20230512
add open_tree(), move_mount()
add /proc/cpuinfo for riscv
fixes and cleanup
# -----BEGIN PGP SIGNATURE-----
#
# iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmReIWcSHGxhdXJlbnRA
# dml2aWVyLmV1AAoJEPMMOL0/L748fNEP/iS0cgOdN89SqruuuxpkBGhbGjJHn/bH
# JkizVkpmX66lH/XPDFonKIlEF26w93jPzhFO6v7WSOhefhuFoQ19tMsIQxlq14DI
# PQZs1LFmoxPiAfq+F7SQbSjYJBOOApUaqld+Y9DZJjYQvByHAwexpnCBUGvqel+n
# EqdAmKTD5hxdieb6pPSFglB1DR6DHD6vDreuC7u8F8unC3Vuf3t+Za0jgGMq47Gi
# o1IqeoLWtYcjXMFrAOX/wgUHWOTt6jCcfFMOs4ObF2T9fZAmo/lNyF6v0++qYnMF
# jYp2LS/nMa4L/Vs26P+R3CJDz9K7MEPM/Eg0XHufZAK5lxdBauhcgrivCNgSbfWt
# HNAnJwNtBdT1jFAOUsHBk6KrhTo33GwoXKG04A/E7ADPebkoTnsnhnzeUn47fS5l
# dYDmzv6aXOScmMy7lKRJLo9sM/5LUMCge7PZwpfI4C/4JUlE5mH2wIpvE4PdFd4+
# id8V7qFrtIb46Q4I2vLjyN9HJ+cXmJ4fmzgpoGERd1Wj+AxCe+tLIl0Ix586v0zY
# DV1cV6Me8dTsOAXV3UdHlXJeIjQ3cXttKvZ3eAn+P7S8KdX4OlMA4lUalAIZcSPh
# ThoON1bk+z46etWdtS+PfV334CenZEQkborAKB8ASffgGNii0gyjswlfSxA0u4SA
# 0/q8p/dNQsQH
# =kg+2
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 12 May 2023 12:22:15 PM BST
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [undefined]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu:
linux-user: fix getgroups/setgroups allocations
linux-user: Fix mips fp64 executables loading
linux-user: Don't require PROT_READ for mincore
linux-user: Add new flag VERIFY_NONE
linux-user/main: Use list_cpus() instead of cpu_list()
linux-user: Add open_tree() syscall
linux-user: Add move_mount() syscall
linux-user: report ENOTTY for unknown ioctls
linux-user: Emulate /proc/cpuinfo output for riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5361db7101b02181a51b7b739a2933ac0c8e1ce5
https://github.com/qemu/qemu/commit/5361db7101b02181a51b7b739a2933ac0c8e1ce5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M MAINTAINERS
M docs/system/devices/igb.rst
M docs/system/devices/ivshmem.rst
M docs/system/devices/net.rst
M docs/system/devices/usb.rst
M docs/system/keys.rst
M docs/system/linuxboot.rst
M docs/system/target-i386.rst
M hw/mips/malta.c
M target/arm/Kconfig
R target/arm/arm_ldst.h
M target/arm/gdbstub64.c
R target/arm/helper-a64.h
R target/arm/helper-mve.h
R target/arm/helper-sme.h
R target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/ptw.c
R target/arm/sve_ldst_internal.h
A target/arm/tcg/arm_ldst.h
A target/arm/tcg/helper-a64.h
A target/arm/tcg/helper-mve.h
A target/arm/tcg/helper-sme.h
A target/arm/tcg/helper-sve.h
M target/arm/tcg/pauth_helper.c
A target/arm/tcg/sve_ldst_internal.h
A target/arm/tcg/translate-a32.h
R target/arm/translate-a32.h
M tests/qtest/cdrom-test.c
M ui/console.c
Log Message:
-----------
Merge tag 'pull-target-arm-20230512' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* More refactoring of files into tcg/
* Don't allow stage 2 page table walks to downgrade to NS
* Fix handling of SW and NSW bits for stage 2 walks
* MAINTAINERS: Update Akihiko Odaki's email address
* ui: Fix pixel colour channel order for PNG screenshots
* docs: Remove unused weirdly-named cross-reference targets
* hw/mips/malta: Fix minor dead code issue
* Fixes for the "allow CONFIG_TCG=n" changes
* tests/qtest: Don't run cdrom boot tests if no accelerator is present
* target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmReXCMZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3hUTEACL2MrxSmAssP0pZ6qQGqgM
# uKz1aL8WDz2MyDzgt0jvy+bRw6081k4iyFGLpsHPWjAm9lipwVSIbVKsvJOrXxpJ
# LDfllv6XtGF/W0o0NDB2KRjC9ro71JoWWJrvjXPYImid3cBfmSdgyR3eUgOLbfj6
# qT2U9nKk8heRDXVb/BWorvajbZm0GaIypL4wUh3Ab2W17Fot073QZLpwcI7LQTJR
# RkyyknzCfaN0xLQ4wEsqJjfLpxgnB2XubSXtG86or7kiIC5/sPivE7fDj0BK9hAM
# Lpe/fkqBrCMGH3K4AC6zDWHQyDtrUT8IKTjR/kIdkjTBcVSzTyfiGob8/Tlmsez9
# rv0vrRJdNguJVo7zd2F17HmsPf4fznS56Yz392kY16LEV/OC6gISz2Sp7qdgbqHA
# ArEFQaYDi2AE/u2wBduZV+SVgZaDrEVtTDo5aw7ms3ebnaMFjB1YmMdp0vZE0p89
# Nlx2ooh0DsYOSLHGWjgRmegGpHgiWcYIW2Ekj2BvzB11fH9lbxvHZMavYNGugdh+
# Z0zj3qRp58+Qg7529AvLe9BWSGhIg6GIuTR/ROux6UL0EV6IZNcjtXQhEOSBqFMF
# uRjcbWOKZtPcpgC7aJj8JeeuzzkaqvWziw8S/ajRes65PvCCQvlxNlJfv49MkS5S
# iMYyID863vocejQpGMqs6A==
# =D3ev
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 12 May 2023 04:32:51 PM BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20230512' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
tests/qtest: Don't run cdrom boot tests if no accelerator is present
target/arm: Select CONFIG_ARM_V7M when TCG is enabled
target/arm: Select SEMIHOSTING when using TCG
hw/mips/malta: Fix minor dead code issue
docs: Remove unused weirdly-named cross-reference targets
ui: Fix pixel colour channel order for PNG screenshots
MAINTAINERS: Update Akihiko Odaki's email address
target/arm: Fix handling of SW and NSW bits for stage 2 walks
target/arm: Don't allow stage 2 page table walks to downgrade to NS
target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/
target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/278238505d28...5361db7101b0
- [Qemu-commits] [qemu/qemu] f9e2b9: linux-user: Emulate /proc/cpuinfo output for riscv,
Richard Henderson <=