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[Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation
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From: |
Clemens Kolbitsch |
|
Subject: |
[Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation |
|
Date: |
Tue, 18 Mar 2008 09:19:04 +0100 |
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User-agent: |
KMail/1.9.6 (enterprise 0.20070907.709405) |
Patch #9: (final)
These three files are taken from the ath5k reverse engineering project and
include definitions
used inside the driver/IO code. Again, license and documentation unchanged.
There are many definitions that might not be used, but eliminating those is a
time consuming
process...
diff -Naur qemu/hw/ath5k.h qemu-altered/hw/ath5k.h
--- qemu/hw/ath5k.h 1970-01-01 01:00:00.000000000 +0100
+++ qemu-altered/hw/ath5k.h 2008-03-01 13:20:07.000000000 +0100
@@ -0,0 +1,887 @@
+/*
+ * Copyright (c) 2004-2007 Reyk Floeter <address@hidden>
+ * Copyright (c) 2006-2007 Nick Kossifidis <address@hidden>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id$
+ */
+
+/*
+ * HAL interface for Atheros Wireless LAN devices.
+ *
+ * ar5k is a free replacement of the binary-only HAL used by some drivers
+ * for Atheros chipsets. While using a different ABI, it tries to be
+ * source-compatible with the original (non-free) HAL interface.
+ *
+ * Many thanks to various contributors who supported the development of
+ * ar5k with hard work and useful information. And, of course, for all the
+ * people who encouraged me to continue this work which has been based
+ * on my initial approach found on http://team.vantronix.net/ar5k/.
+ */
+
+#ifndef _AR5K_H
+#define _AR5K_H
+
+
+
+
+/*
+ * Device tracing
+ */
+
+#define AR5K_TRACE_PRINTF(_trace) AR5K_PRINTF(_trace)
+
+
+
+
+
+
+/****************************\
+ GENERIC DRIVER DEFINITIONS
+\****************************/
+
+/*
+ * C doesn't support boolean ;-(
+ * TODO: See if there is a bool definition somewere else
+ * in the kernel, we shouldn't redefine it if it does...
+ */
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+typedef u_int8_t AR5K_BOOL;
+
+/*
+ * Error codes reported from HAL to the driver
+ */
+typedef enum {
+ AR5K_OK = 0, /* Everything went O.K.*/
+ AR5K_ENOMEM = 1, /* Unable to allocate memory for ath_hal*/
+ AR5K_EIO = 2, /* Hardware I/O Error*/
+ AR5K_EELOCKED = 3, /* Unable to access EEPROM*/
+ AR5K_EEBADSUM = 4, /* Invalid EEPROM checksum*/
+ AR5K_EEREAD = 5, /* Unable to get device caps from EEPROM */
+ AR5K_EEBADMAC = 6, /* Unable to read MAC address from EEPROM */
+ AR5K_EINVAL = 7, /* Invalid parameter to function */
+ AR5K_ENOTSUPP = 8, /* Hardware revision not supported */
+ AR5K_EINPROGRESS= 9, /* Unexpected error ocured during process */
+} AR5K_STATUS;
+
+/*
+ * Some tuneable values (these should be changeable by the user)
+ */
+#define AR5K_TUNE_DMA_BEACON_RESP 2
+#define AR5K_TUNE_SW_BEACON_RESP 10
+#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
+#define AR5K_TUNE_RADAR_ALERT FALSE
+#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
+#define AR5K_TUNE_MAX_TX_FIFO_THRES ((MAX_PDU_LENGTH / 64) + 1)
+#define AR5K_TUNE_RSSI_THRES 1792
+#define AR5K_TUNE_REGISTER_TIMEOUT 20000
+#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
+#define AR5K_TUNE_BEACON_INTERVAL 100
+#define AR5K_TUNE_AIFS 2
+#define AR5K_TUNE_AIFS_11B 2
+#define AR5K_TUNE_AIFS_XR 0
+#define AR5K_TUNE_CWMIN 15
+#define AR5K_TUNE_CWMIN_11B 31
+#define AR5K_TUNE_CWMIN_XR 3
+#define AR5K_TUNE_CWMAX 1023
+#define AR5K_TUNE_CWMAX_11B 1023
+#define AR5K_TUNE_CWMAX_XR 7
+#define AR5K_TUNE_NOISE_FLOOR -72
+#define AR5K_TUNE_MAX_TXPOWER 60
+#define AR5K_TUNE_DEFAULT_TXPOWER 30
+#define AR5K_TUNE_TPC_TXPOWER TRUE
+#define AR5K_TUNE_ANT_DIVERSITY TRUE
+#define AR5K_TUNE_HWTXTRIES 4
+
+/* token to use for aifs, cwmin, cwmax in MadWiFi */
+#define AR5K_TXQ_USEDEFAULT ((u_int32_t) -1)
+
+#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */
+#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */
+static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff,
0xff, 0xff, 0xff };
+//#define etherbroadcastaddr 0xff
+
+
+
+
+/*****************************\
+ GENERIC CHIPSET DEFINITIONS
+\*****************************/
+
+/* MAC Chips*/
+enum ath5k_version {
+ AR5K_AR5210 = 0,
+ AR5K_AR5211 = 1,
+ AR5K_AR5212 = 2,
+};
+
+/*PHY Chips*/
+enum ath5k_radio {
+ AR5K_AR5110 = 0,
+ AR5K_AR5111 = 1,
+ AR5K_AR5112 = 2,
+};
+
+/*
+ * Common silicon revision/version values
+ */
+enum ath5k_srev_type {
+ AR5K_VERSION_VER,
+ AR5K_VERSION_REV,
+ AR5K_VERSION_RAD,
+ AR5K_VERSION_DEV
+};
+
+struct ath5k_srev_name {
+ const char *sr_name;
+ enum ath5k_srev_type sr_type;
+ u_int sr_val;
+};
+
+#define AR5K_SREV_NAME { \
+ { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \
+ { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \
+ { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\
+ { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\
+ { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \
+ { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \
+ { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \
+ { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \
+ { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \
+ { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \
+ { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \
+ { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \
+ { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \
+ { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \
+ { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \
+ { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \
+ { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \
+ { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \
+ { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \
+ { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \
+}
+
+#define AR5K_SREV_UNKNOWN 0xffff
+
+#define AR5K_SREV_VER_AR5210 0x00
+#define AR5K_SREV_VER_AR5311 0x10
+#define AR5K_SREV_VER_AR5311A 0x20
+#define AR5K_SREV_VER_AR5311B 0x30
+#define AR5K_SREV_VER_AR5211 0x40
+#define AR5K_SREV_VER_AR5212 0x50
+#define AR5K_SREV_VER_AR5213 0x55
+#define AR5K_SREV_VER_UNSUPP 0x60
+
+#define AR5K_SREV_RAD_5110 0x00
+#define AR5K_SREV_RAD_5111 0x10
+#define AR5K_SREV_RAD_5111A 0x15
+#define AR5K_SREV_RAD_2111 0x20
+#define AR5K_SREV_RAD_5112 0x30
+#define AR5K_SREV_RAD_5112A 0x35
+#define AR5K_SREV_RAD_2112 0x40
+#define AR5K_SREV_RAD_2112A 0x45
+#define AR5K_SREV_RAD_UNSUPP 0x50
+
+
+
+
+/****************\
+ TX DEFINITIONS
+\****************/
+
+/*
+ * Tx Descriptor
+ */
+struct ath_tx_status {
+ u_int16_t ts_seqnum;
+ u_int16_t ts_tstamp;
+ u_int8_t ts_status;
+ u_int8_t ts_rate;
+ int8_t ts_rssi;
+ u_int8_t ts_shortretry;
+ u_int8_t ts_longretry;
+ u_int8_t ts_virtcol;
+ u_int8_t ts_antenna;
+};
+
+#define AR5K_TXSTAT_ALTRATE 0x80
+#define AR5K_TXERR_XRETRY 0x01
+#define AR5K_TXERR_FILT 0x02
+#define AR5K_TXERR_FIFO 0x04
+
+/*
+ * Queue types used to classify tx queues.
+ */
+typedef enum {
+ AR5K_TX_QUEUE_INACTIVE = 0,/*This queue is not used -see
ath_hal_releasetxqueue*/
+ AR5K_TX_QUEUE_DATA, /*A normal data queue*/
+ AR5K_TX_QUEUE_XR_DATA, /*An XR-data queue*/
+ AR5K_TX_QUEUE_BEACON, /*The beacon queue*/
+ AR5K_TX_QUEUE_CAB, /*The ater-beacon queue*/
+ AR5K_TX_QUEUE_UAPSD, /*Unscheduled Automatic Power Save Delivery
queue*/
+} AR5K_TX_QUEUE;
+
+#define AR5K_NUM_TX_QUEUES 10
+
+/*
+ * Queue syb-types to classify normal data queues.
+ * These are the 4 Access Categories as defined in
+ * WME spec. 0 is the lowest priority and 4 is the
+ * highest. Normal data that hasn't been classified
+ * goes to the Best Effort AC.
+ */
+typedef enum {
+ AR5K_WME_AC_BK = 0, /*Background traffic*/
+ AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
+ AR5K_WME_AC_VI, /*Video traffic*/
+ AR5K_WME_AC_VO, /*Voice traffic*/
+} AR5K_TX_QUEUE_SUBTYPE;
+
+/*
+ * Queue ID numbers as returned by the HAL, each number
+ * represents a hw queue. If hw does not support hw queues
+ * (eg 5210/5211) all data goes in one queue. These match
+ * d80211 definitions (net80211/MadWiFi don't use them).
+ */
+typedef enum {
+ AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
+ AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
+ AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink
Voice Protocol*/
+ AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
+ AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
+ AR5K_TX_QUEUE_ID_UAPSD = 8,
+ AR5K_TX_QUEUE_ID_XR_DATA = 9,
+} AR5K_TX_QUEUE_ID;
+
+
+/*
+ * Flags to set hw queue's parameters...
+ */
+#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and
TXERR interrupts -not used- */
+#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC
interrupt -not implemented- */
+#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 /* Disable random
post-backoff */
+#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 /* Enable hw
compression -not implemented-*/
+#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 /* Enable ready
time expiry policy (?)*/
+#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 /* Enable
backoff while bursting */
+#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 /* Disable
backoff while bursting */
+#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0080 /* Enable TXEOL
interrupt -not implemented-*/
+
+/*
+ * A struct to hold tx queue's parameters
+ */
+typedef struct {
+ AR5K_TX_QUEUE tqi_type; /* See AR5K_TX_QUEUE */
+ AR5K_TX_QUEUE_SUBTYPE tqi_subtype; /* See
AR5K_TX_QUEUE_SUBTYPE */
+ u_int16_t tqi_flags; /* Tx queue flags (see
above) */
+ u_int32_t tqi_aifs; /* Arbitrated
Interframe Space */
+ int32_t tqi_cw_min; /* Minimum Contention
Window */
+ int32_t tqi_cw_max; /* Maximum Contention
Window */
+ u_int32_t tqi_cbr_period; /* Constant bit rate
period */
+ u_int32_t tqi_cbr_overflow_limit;
+ u_int32_t tqi_burst_time;
+ u_int32_t tqi_ready_time; /* Not used */
+ u_int32_t tqi_comp_buffer;/* Compression Buffer's
phys addr */
+} AR5K_TXQ_INFO;
+
+/*
+ * Transmit packet types.
+ * These are not fully used inside OpenHAL yet
+ */
+typedef enum {
+ AR5K_PKT_TYPE_NORMAL = 0,
+ AR5K_PKT_TYPE_ATIM = 1,
+ AR5K_PKT_TYPE_PSPOLL = 2,
+ AR5K_PKT_TYPE_BEACON = 3,
+ AR5K_PKT_TYPE_PROBE_RESP = 4,
+ AR5K_PKT_TYPE_PIFS = 5,
+} AR5K_PKT_TYPE;
+
+/*
+ * TX power and TPC settings
+ */
+#define AR5K_TXPOWER_OFDM(_r, _v) ( \
+ ((0 & 1) << ((_v) + 6)) | \
+ (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
+)
+
+#define AR5K_TXPOWER_CCK(_r, _v) ( \
+ (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
+)
+
+/*
+ * Used to compute TX times
+ */
+#define AR5K_CCK_SIFS_TIME 10
+#define AR5K_CCK_PREAMBLE_BITS 144
+#define AR5K_CCK_PLCP_BITS 48
+
+#define AR5K_OFDM_SIFS_TIME 16
+#define AR5K_OFDM_PREAMBLE_TIME 20
+#define AR5K_OFDM_PLCP_BITS 22
+#define AR5K_OFDM_SYMBOL_TIME 4
+
+#define AR5K_TURBO_SIFS_TIME 8
+#define AR5K_TURBO_PREAMBLE_TIME 14
+#define AR5K_TURBO_PLCP_BITS 22
+#define AR5K_TURBO_SYMBOL_TIME 4
+
+#define AR5K_XR_SIFS_TIME 16
+#define AR5K_XR_PLCP_BITS 22
+#define AR5K_XR_SYMBOL_TIME 4
+
+/* CCK */
+#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3)
+
+#define AR5K_CCK_PHY_TIME(_sp) (_sp ? \
+ ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \
+ (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))
+
+#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \
+ AR5K_CCK_PHY_TIME(_sp) + \
+ ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \
+ AR5K_CCK_SIFS_TIME
+
+/* OFDM */
+#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
+
+#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
+ AR5K_OFDM_SYMBOL_TIME) / 1000)
+
+#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
+
+#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \
+ howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))
+
+#define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \
+ AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \
+ (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)
+
+/* TURBO */
+#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
+
+#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \
+ AR5K_TURBO_SYMBOL_TIME) / 1000)
+
+#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
+
+#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \
+ howmany(AR5K_TURBO_NUM_BITS(_frmlen), \
+ AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))
+
+#define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \
+ AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \
+ (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)
+
+/* eXtendent Range (?)*/
+#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)
+
+#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
+ AR5K_XR_SYMBOL_TIME) / 1000)
+
+#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3))
+
+#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \
+ howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))
+
+#define AR5K_XR_TX_TIME(_kbps, _frmlen) \
+ AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \
+ (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)
+
+/*
+ * DMA size definitions (2^n+2)
+ */
+typedef enum {
+ AR5K_DMASIZE_4B = 0,
+ AR5K_DMASIZE_8B,
+ AR5K_DMASIZE_16B,
+ AR5K_DMASIZE_32B,
+ AR5K_DMASIZE_64B,
+ AR5K_DMASIZE_128B,
+ AR5K_DMASIZE_256B,
+ AR5K_DMASIZE_512B
+} ath5k_dmasize_t;
+
+
+
+/****************\
+ RX DEFINITIONS
+\****************/
+
+/*
+ * Rx Descriptor
+ */
+struct ath_rx_status {
+ u_int16_t rs_datalen;
+ u_int16_t rs_tstamp;
+ u_int8_t rs_status;
+ u_int8_t rs_phyerr;
+ int8_t rs_rssi;
+ u_int8_t rs_keyix;
+ u_int8_t rs_rate;
+ u_int8_t rs_antenna;
+ u_int8_t rs_more;
+};
+
+#define AR5K_RXERR_CRC 0x01
+#define AR5K_RXERR_PHY 0x02
+#define AR5K_RXERR_FIFO 0x04
+#define AR5K_RXERR_DECRYPT 0x08
+#define AR5K_RXERR_MIC 0x10
+#define AR5K_RXKEYIX_INVALID ((u_int8_t) - 1)
+#define AR5K_TXKEYIX_INVALID ((u_int32_t) - 1)
+
+/*
+ * RX filters
+ * Most of them are not yet used inside OpenHAL
+ */
+#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter
unicast frames */
+#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter
multicast frames */
+#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter
broadcast frames */
+#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter
control frames */
+#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter
beacon frames */
+#define AR5K_RX_FILTER_PROM 0x00000020 /* Set
promiscuous mode */
+#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter
XR poll frame */
+#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter
probe requests */
+#define AR5K_RX_FILTER_PHYERROR 0x00000100 /* Don't filter
phy errors */
+#define AR5K_RX_FILTER_PHYRADAR 0x00000200 /* Don't filter
phy radar errors*/
+
+typedef struct {
+ u_int32_t ackrcv_bad;
+ u_int32_t rts_bad;
+ u_int32_t rts_good;
+ u_int32_t fcs_bad;
+ u_int32_t beacons;
+} AR5K_MIB_STATS;
+
+
+
+
+/**************************\
+ BEACON TIMERS DEFINITIONS
+\**************************/
+
+#define AR5K_BEACON_PERIOD 0x0000ffff
+#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
+#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
+
+/*
+ * Per-station beacon timer state.
+ */
+typedef struct {
+ u_int32_t bs_next_beacon;
+ u_int32_t bs_next_dtim;
+ u_int32_t bs_interval; /*in TU's -see
net80211/ieee80211_var.h-
+ can also include the above
flags*/
+ u_int8_t bs_dtim_period;
+ u_int8_t bs_cfp_period;
+ u_int16_t bs_cfp_max_duration; /*if non-zero hw is setup to
coexist with
+ a Point Coordination Function
capable AP*/
+ u_int16_t bs_cfp_du_remain;
+ u_int16_t bs_tim_offset;
+ u_int16_t bs_sleep_duration;
+ u_int16_t bs_bmiss_threshold;
+ u_int32_t bs_cfp_next;
+} AR5K_BEACON_STATE;
+
+
+
+
+/********************\
+ COMMON DEFINITIONS
+\********************/
+
+/*
+ * Atheros descriptor
+ */
+struct ath_desc {
+ u_int32_t ds_link;
+ u_int32_t ds_data;
+ u_int32_t ds_ctl0;
+ u_int32_t ds_ctl1;
+ u_int32_t ds_hw[4];
+
+ union {
+ struct ath_rx_status rx;
+ struct ath_tx_status tx;
+ } ds_us;
+
+#define ds_rxstat ds_us.rx
+#define ds_txstat ds_us.tx
+
+} __packed;
+
+#define AR5K_RXDESC_INTREQ 0x0020
+
+#define AR5K_TXDESC_CLRDMASK 0x0001
+#define AR5K_TXDESC_NOACK 0x0002
+#define AR5K_TXDESC_RTSENA 0x0004
+#define AR5K_TXDESC_CTSENA 0x0008
+#define AR5K_TXDESC_INTREQ 0x0010
+#define AR5K_TXDESC_VEOL 0x0020
+
+/*
+ * 802.11 operating modes...
+ */
+#define AR5K_MODE_11A 0x01
+#define AR5K_MODE_11B 0x02
+#define AR5K_MODE_11G 0x04
+#define AR5K_MODE_TURBO 0x08
+#define AR5K_MODE_108G 0x16
+#define AR5K_MODE_XR 0x32
+#define AR5K_MODE_ALL (AR5K_MODE_11A| \
+ AR5K_MODE_11B| \
+ AR5K_MODE_11G| \
+ AR5K_MODE_TURBO|\
+ AR5K_MODE_108G| \
+ AR5K_MODE_XR)
+
+/*
+ * Channel definitions
+ */
+typedef struct {
+ u_int16_t freq; /* setting in Mhz */
+ u_int16_t channel_flags;
+ u_int8_t private_flags; /* not used in OpenHAL yet*/
+} AR5K_CHANNEL;
+
+#define AR5K_SLOT_TIME_9 396
+#define AR5K_SLOT_TIME_20 880
+#define AR5K_SLOT_TIME_MAX 0xffff
+
+/* channel_flags */
+#define CHANNEL_CW_INT 0x0008 /* Contention Window interference
detected */
+#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
+#define CHANNEL_CCK 0x0020 /* CCK channel */
+#define CHANNEL_OFDM 0x0040 /* OFDM channel */
+#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
+#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
+#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
+#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g
operation)*/
+#define CHANNEL_XR 0x0800 /* XR channel */
+
+#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
+#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
+#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
+//#ifdef notdef
+#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
+//#else
+//#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
+//#endif
+#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_108A CHANNEL_T
+#define CHANNEL_108G CHANNEL_TG
+#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
+
+#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ |\
+ CHANNEL_5GHZ | CHANNEL_TURBO)
+
+#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
+#define CHANNEL_MODES CHANNEL_ALL
+
+/*
+ * Used internaly in OpenHAL (ar5211.c/ar5212.c
+ * for reset_tx_queue). Also see struct AR5K_CHANNEL.
+ */
+#define IS_CHAN_XR(_c) \
+ ((_c.channel_flags & CHANNEL_XR) != 0)
+
+#define IS_CHAN_B(_c) \
+ ((_c.channel_flags & CHANNEL_B) != 0)
+
+typedef enum {
+ AR5K_CHIP_5GHZ = CHANNEL_5GHZ,
+ AR5K_CHIP_2GHZ = CHANNEL_2GHZ,
+} AR5K_CHIP;
+
+/*
+ * The following structure will be used to map 2GHz channels to
+ * 5GHz Atheros channels.
+ */
+struct ath5k_athchan_2ghz {
+ u_int32_t a2_flags;
+ u_int16_t a2_athchan;
+};
+
+/*
+ * Rate definitions
+ */
+
+#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/
+
+typedef struct {
+ u_int8_t valid; /* Valid for rate control */
+ u_int32_t modulation;
+ u_int16_t rate_kbps;
+ u_int8_t rate_code; /* Rate mapping for h/w descriptors */
+ u_int8_t dot11_rate;
+ u_int8_t control_rate;
+ u_int16_t lp_ack_duration;/* long preamble ACK duration */
+ u_int16_t sp_ack_duration;/* short preamble ACK duration*/
+} AR5K_RATE;
+
+typedef struct {
+ u_int16_t rate_count;
+ u_int8_t rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping
*/
+ AR5K_RATE rates[AR5K_MAX_RATES];
+} AR5K_RATE_TABLE;
+
+/*
+ * Rate tables...
+ */
+#define AR5K_RATES_11A { 8, { \
+ 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
+ 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
+ 255, 255, 255, 255, 255, 255, 255, 255 }, { \
+ { 1, MODULATION_OFDM, 6000, 11, 140, 0 }, \
+ { 1, MODULATION_OFDM, 9000, 15, 18, 0 }, \
+ { 1, MODULATION_OFDM, 12000, 10, 152, 2 }, \
+ { 1, MODULATION_OFDM, 18000, 14, 36, 2 }, \
+ { 1, MODULATION_OFDM, 24000, 9, 176, 4 }, \
+ { 1, MODULATION_OFDM, 36000, 13, 72, 4 }, \
+ { 1, MODULATION_OFDM, 48000, 8, 96, 4 }, \
+ { 1, MODULATION_OFDM, 54000, 12, 108, 4 } } \
+}
+
+#define AR5K_RATES_11B { 4, { \
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
+ 3, 2, 1, 0, 255, 255, 255, 255 }, { \
+ { 1, MODULATION_CCK, 1000, 27, 130, 0 }, \
+ { 1, MODULATION_CCK, 2000, 26, 132, 1 }, \
+ { 1, MODULATION_CCK, 5500, 25, 139, 1 }, \
+ { 1, MODULATION_CCK, 11000, 24, 150, 1 } } \
+}
+
+#define AR5K_RATES_11G { 12, { \
+ 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \
+ 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
+ 3, 2, 1, 0, 255, 255, 255, 255 }, { \
+ { 1, MODULATION_CCK, 1000, 27, 2, 0 }, \
+ { 1, MODULATION_CCK, 2000, 26, 4, 1 }, \
+ { 1, MODULATION_CCK, 5500, 25, 11, 1 }, \
+ { 1, MODULATION_CCK, 11000, 24, 22, 1 }, \
+ { 0, MODULATION_OFDM, 6000, 11, 12, 4 }, \
+ { 0, MODULATION_OFDM, 9000, 15, 18, 4 }, \
+ { 1, MODULATION_OFDM, 12000, 10, 24, 6 }, \
+ { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \
+ { 1, MODULATION_OFDM, 24000, 9, 48, 8 }, \
+ { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \
+ { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \
+ { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \
+}
+
+#define AR5K_RATES_TURBO { 8, { \
+ 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
+ 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
+ 255, 255, 255, 255, 255, 255, 255, 255 }, { \
+ { 1, MODULATION_TURBO, 6000, 11, 140, 0 }, \
+ { 1, MODULATION_TURBO, 9000, 15, 18, 0 }, \
+ { 1, MODULATION_TURBO, 12000, 10, 152, 2 }, \
+ { 1, MODULATION_TURBO, 18000, 14, 36, 2 }, \
+ { 1, MODULATION_TURBO, 24000, 9, 176, 4 }, \
+ { 1, MODULATION_TURBO, 36000, 13, 72, 4 }, \
+ { 1, MODULATION_TURBO, 48000, 8, 96, 4 }, \
+ { 1, MODULATION_TURBO, 54000, 12, 108, 4 } } \
+}
+
+#define AR5K_RATES_XR { 12, { \
+ 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \
+ 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
+ 255, 255, 255, 255, 255, 255, 255, 255 }, { \
+ { 1, MODULATION_XR, 500, 7, 129, 0 }, \
+ { 1, MODULATION_XR, 1000, 2, 139, 1 }, \
+ { 1, MODULATION_XR, 2000, 6, 150, 2 }, \
+ { 1, MODULATION_XR, 3000, 1, 150, 3 }, \
+ { 1, MODULATION_OFDM, 6000, 11, 140, 4 }, \
+ { 1, MODULATION_OFDM, 9000, 15, 18, 4 }, \
+ { 1, MODULATION_OFDM, 12000, 10, 152, 6 }, \
+ { 1, MODULATION_OFDM, 18000, 14, 36, 6 }, \
+ { 1, MODULATION_OFDM, 24000, 9, 176, 8 }, \
+ { 1, MODULATION_OFDM, 36000, 13, 72, 8 }, \
+ { 1, MODULATION_OFDM, 48000, 8, 96, 8 }, \
+ { 1, MODULATION_OFDM, 54000, 12, 108, 8 } } \
+}
+
+/*
+ * Crypto definitions
+ */
+
+/* key types */
+typedef enum {
+ AR5K_CIPHER_WEP = 0,
+ AR5K_CIPHER_AES_OCB = 1,
+ AR5K_CIPHER_AES_CCM = 2,
+ AR5K_CIPHER_CKIP = 3,
+ AR5K_CIPHER_TKIP = 4,
+ AR5K_CIPHER_CLR = 5, /* no encryption */
+ AR5K_CIPHER_MIC = 127 /* used for Message
+ Integrity Code */
+} AR5K_CIPHER;
+
+#define AR5K_KEYVAL_LENGTH_40 5
+#define AR5K_KEYVAL_LENGTH_104 13
+#define AR5K_KEYVAL_LENGTH_128 16
+#define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128
+
+typedef struct {
+ int wk_len; /* key's length */
+ u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX];
+ u_int8_t wk_type; /* see above */
+ u_int8_t wk_mic[8]; /* TKIP MIC key */
+} AR5K_KEYVAL;
+
+
+
+/***********************\
+ HW RELATED DEFINITIONS
+\***********************/
+
+/*
+ * Misc definitions
+ */
+#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
+
+#define AR5K_ASSERT_ENTRY(_e, _s) do { \
+ if (_e >= _s) \
+ return (FALSE); \
+} while (0)
+
+
+typedef struct {
+ u_int32_t ns_avgbrssi; /* average beacon rssi */
+ u_int32_t ns_avgrssi; /* average data rssi */
+ u_int32_t ns_avgtxrssi; /* average tx rssi */
+} AR5K_NODE_STATS;
+
+typedef enum {
+ AR5K_ANT_VARIABLE = 0, /* variable by programming */
+ AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */
+ AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */
+ AR5K_ANT_MAX = 3,
+} AR5K_ANT_SETTING;
+
+/*
+ * HAL interrupt abstraction
+ */
+
+/*
+ * These are maped to take advantage of some common bits
+ * between the MAC chips, to be able to set intr properties
+ * easier. Some of them are not used yet inside OpenHAL.
+ */
+typedef enum {
+ AR5K_INT_RX = 0x00000001,
+ AR5K_INT_RXDESC = 0x00000002,
+ AR5K_INT_RXNOFRM = 0x00000008,
+ AR5K_INT_RXEOL = 0x00000010,
+ AR5K_INT_RXORN = 0x00000020,
+ AR5K_INT_TX = 0x00000040,
+ AR5K_INT_TXDESC = 0x00000080,
+ AR5K_INT_TXURN = 0x00000800,
+ AR5K_INT_MIB = 0x00001000,
+ AR5K_INT_RXPHY = 0x00004000,
+ AR5K_INT_RXKCM = 0x00008000,
+ AR5K_INT_SWBA = 0x00010000,
+ AR5K_INT_BMISS = 0x00040000,
+ AR5K_INT_BNR = 0x00100000,
+ AR5K_INT_GPIO = 0x01000000,
+ AR5K_INT_FATAL = 0x40000000,
+ AR5K_INT_GLOBAL = 0x80000000,
+
+ /*A sum of all the common bits*/
+ AR5K_INT_COMMON = AR5K_INT_RXNOFRM
+ | AR5K_INT_RXDESC
+ | AR5K_INT_RXEOL
+ | AR5K_INT_RXORN
+ | AR5K_INT_TXURN
+ | AR5K_INT_TXDESC
+ | AR5K_INT_MIB
+ | AR5K_INT_RXPHY
+ | AR5K_INT_RXKCM
+ | AR5K_INT_SWBA
+ | AR5K_INT_BMISS
+ | AR5K_INT_GPIO,
+ AR5K_INT_NOCARD = 0xffffffff /*Declare that the card
+ has been removed*/
+} AR5K_INT;
+
+/*
+ * Power management
+ */
+typedef enum {
+ AR5K_PM_UNDEFINED = 0,
+ AR5K_PM_AUTO,
+ AR5K_PM_AWAKE,
+ AR5K_PM_FULL_SLEEP,
+ AR5K_PM_NETWORK_SLEEP,
+} AR5K_POWER_MODE;
+
+
+/*
+ * LED states
+ */
+typedef int AR5K_LED_STATE;
+
+/*
+ * These match net80211 definitions (not used in
+ * d80211).
+ */
+#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
+#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
+#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
+#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
+#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
+
+/* GPIO-controlled software LED */
+#define AR5K_SOFTLED_PIN 0
+#define AR5K_SOFTLED_ON 0
+#define AR5K_SOFTLED_OFF 1
+
+/*
+ * Chipset capabilities -see ath_hal_getcapability-
+ * get_capability function is not yet fully implemented
+ * in OpenHAL so most of these don't work yet...
+ */
+typedef enum {
+ AR5K_CAP_REG_DMN = 0, /* Used to get current reg.
domain id */
+ AR5K_CAP_CIPHER = 1, /* Can handle encryption */
+ AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in
hardware */
+ AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
+ AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
+ AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
+ AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw
txqueues */
+ AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
+ AR5K_CAP_COMPRESSION = 8, /* Supports compression */
+ AR5K_CAP_BURST = 9, /* Supports packet bursting */
+ AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
+ AR5K_CAP_TXPOW = 11, /* Used to get global tx power
limit */
+ AR5K_CAP_TPC = 12, /* Can do per-packet tx power
control (needed for 802.11a) */
+ AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
+ AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key
search */
+ AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
+ AR5K_CAP_XR = 16, /* Supports XR mode */
+ AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using
WMM */
+ AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels
*/
+ AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate
channels */
+ AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
+} AR5K_CAPABILITY_TYPE;
+
+
+#endif /* _AR5K_H */
diff -Naur qemu/hw/ath5k_hw.h qemu-altered/hw/ath5k_hw.h
--- qemu/hw/ath5k_hw.h 1970-01-01 01:00:00.000000000 +0100
+++ qemu-altered/hw/ath5k_hw.h 2008-03-01 13:20:07.000000000 +0100
@@ -0,0 +1,1939 @@
+/*
+ * Copyright (c) 2004-2007 Reyk Floeter <address@hidden>
+ * Copyright (c) 2006-2007 Nick Kossifidis <address@hidden>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id$
+ */
+
+/*
+ * Gain settings
+ */
+
+typedef enum {
+ AR5K_RFGAIN_INACTIVE = 0,
+ AR5K_RFGAIN_READ_REQUESTED,
+ AR5K_RFGAIN_NEED_CHANGE,
+} AR5K_RFGAIN;
+
+#define AR5K_GAIN_CRN_FIX_BITS_5111 4
+#define AR5K_GAIN_CRN_FIX_BITS_5112 7
+#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
+#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
+#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
+#define AR5K_GAIN_CCK_PROBE_CORR 5
+#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
+#define AR5K_GAIN_STEP_COUNT 10
+#define AR5K_GAIN_PARAM_TX_CLIP 0
+#define AR5K_GAIN_PARAM_PD_90 1
+#define AR5K_GAIN_PARAM_PD_84 2
+#define AR5K_GAIN_PARAM_GAIN_SEL 3
+#define AR5K_GAIN_PARAM_MIX_ORN 0
+#define AR5K_GAIN_PARAM_PD_138 1
+#define AR5K_GAIN_PARAM_PD_137 2
+#define AR5K_GAIN_PARAM_PD_136 3
+#define AR5K_GAIN_PARAM_PD_132 4
+#define AR5K_GAIN_PARAM_PD_131 5
+#define AR5K_GAIN_PARAM_PD_130 6
+#define AR5K_GAIN_CHECK_ADJUST(_g) \
+ ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
+
+struct ath5k_gain_opt_step {
+ int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
+ int32_t gos_gain;
+};
+
+struct ath5k_gain_opt {
+ u_int32_t go_default;
+ u_int32_t go_steps_count;
+ const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
+};
+
+struct ath5k_gain {
+ u_int32_t g_step_idx;
+ u_int32_t g_current;
+ u_int32_t g_target;
+ u_int32_t g_low;
+ u_int32_t g_high;
+ u_int32_t g_f_corr;
+ u_int32_t g_active;
+ const struct ath5k_gain_opt_step *g_step;
+};
+
+/*
+ * Gain optimization tables...
+ */
+#define AR5K_AR5111_GAIN_OPT { \
+ 4, \
+ 9, \
+ { \
+ { { 4, 1, 1, 1 }, 6 }, \
+ { { 4, 0, 1, 1 }, 4 }, \
+ { { 3, 1, 1, 1 }, 3 }, \
+ { { 4, 0, 0, 1 }, 1 }, \
+ { { 4, 1, 1, 0 }, 0 }, \
+ { { 4, 0, 1, 0 }, -2 }, \
+ { { 3, 1, 1, 0 }, -3 }, \
+ { { 4, 0, 0, 0 }, -4 }, \
+ { { 2, 1, 1, 0 }, -6 } \
+ } \
+}
+
+#define AR5K_AR5112_GAIN_OPT { \
+ 1, \
+ 8, \
+ { \
+ { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \
+ { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \
+ { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \
+ { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \
+ { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \
+ { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \
+ { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \
+ { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \
+ } \
+}
+
+/* Some EEPROM defines */
+#define AR5K_EEPROM_EEP_SCALE 100
+#define AR5K_EEPROM_EEP_DELTA 10
+#define AR5K_EEPROM_N_MODES 3
+#define AR5K_EEPROM_N_5GHZ_CHAN 10
+#define AR5K_EEPROM_N_2GHZ_CHAN 3
+#define AR5K_EEPROM_MAX_CHAN 10
+#define AR5K_EEPROM_N_PCDAC 11
+#define AR5K_EEPROM_N_TEST_FREQ 8
+#define AR5K_EEPROM_N_EDGES 8
+#define AR5K_EEPROM_N_INTERCEPTS 11
+#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
+#define AR5K_EEPROM_PCDAC_M 0x3f
+#define AR5K_EEPROM_PCDAC_START 1
+#define AR5K_EEPROM_PCDAC_STOP 63
+#define AR5K_EEPROM_PCDAC_STEP 1
+#define AR5K_EEPROM_NON_EDGE_M 0x40
+#define AR5K_EEPROM_CHANNEL_POWER 8
+#define AR5K_EEPROM_N_OBDB 4
+#define AR5K_EEPROM_OBDB_DIS 0xffff
+#define AR5K_EEPROM_CHANNEL_DIS 0xff
+#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
+#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
+#define AR5K_EEPROM_MAX_CTLS 32
+#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
+#define AR5K_EEPROM_N_XPD0_POINTS 4
+#define AR5K_EEPROM_N_XPD3_POINTS 3
+#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
+#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
+#define AR5K_EEPROM_POWER_M 0x3f
+#define AR5K_EEPROM_POWER_MIN 0
+#define AR5K_EEPROM_POWER_MAX 3150
+#define AR5K_EEPROM_POWER_STEP 50
+#define AR5K_EEPROM_POWER_TABLE_SIZE 64
+#define AR5K_EEPROM_N_POWER_LOC_11B 4
+#define AR5K_EEPROM_N_POWER_LOC_11G 6
+#define AR5K_EEPROM_I_GAIN 10
+#define AR5K_EEPROM_CCK_OFDM_DELTA 15
+#define AR5K_EEPROM_N_IQ_CAL 2
+
+struct ath5k_eeprom_info {
+ u_int16_t ee_magic;
+ u_int16_t ee_protect;
+ u_int16_t ee_regdomain;
+ u_int16_t ee_version;
+ u_int16_t ee_header;
+ u_int16_t ee_ant_gain;
+ u_int16_t ee_misc0;
+ u_int16_t ee_misc1;
+ u_int16_t ee_cck_ofdm_gain_delta;
+ u_int16_t ee_cck_ofdm_power_delta;
+ u_int16_t ee_scaled_cck_delta;
+ u_int16_t ee_tx_clip;
+ u_int16_t ee_pwd_84;
+ u_int16_t ee_pwd_90;
+ u_int16_t ee_gain_select;
+
+ u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
+ u_int16_t
ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
+ u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
+ u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
+ u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_xpd[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
+ u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES];
+ u_int16_t
ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
+ u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN];
+
+ u_int16_t ee_ctls;
+ u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS];
+
+ int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
+ int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES];
+ int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES];
+};
+
+/*
+ * AR5k register access
+ */
+
+/*Swap RX/TX Descriptor for big endian archs*/
+#if BYTE_ORDER == BIG_ENDIAN
+#define AR5K_INIT_CFG ( \
+ AR5K_CFG_SWTD | AR5K_CFG_SWRD \
+)
+#else
+#define AR5K_INIT_CFG 0x00000000
+#endif
+
+#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(hal, _reg)
+
+#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(hal, _val, _reg)
+
+#define AR5K_REG_SM(_val, _flags) \
+ (((_val) << _flags##_S) & (_flags))
+
+#define AR5K_REG_MS(_val, _flags) \
+ (((_val) & (_flags)) >> _flags##_S)
+
+#define AR5K_REG_WRITE_BITS(_reg, _flags, _val)
\
+ AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \
+ (((_val) << _flags##_S) & (_flags)))
+
+#define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \
+ AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
+
+#define AR5K_REG_ENABLE_BITS(_reg, _flags) \
+ AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
+
+#define AR5K_REG_DISABLE_BITS(_reg, _flags) \
+ AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
+
+#define AR5K_PHY_WRITE(_reg, _val) \
+ AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val)
+
+#define AR5K_PHY_READ(_reg) \
+ AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
+
+#define AR5K_REG_WAIT(_i) \
+ if (_i % 64) \
+ AR5K_DELAY(1);
+
+#define AR5K_EEPROM_READ(_o, _v) { \
+ if ((ret = hal->ah_eeprom_read(hal, (_o), \
+ &(_v))) != 0) \
+ return (ret); \
+}
+
+#define AR5K_EEPROM_READ_HDR(_o, _v) \
+ AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \
+
+/* Read status of selected queue */
+#define AR5K_REG_READ_Q(_reg, _queue) \
+ (AR5K_REG_READ(_reg) & (1 << _queue)) \
+
+#define AR5K_REG_WRITE_Q(_reg, _queue) \
+ AR5K_REG_WRITE(_reg, (1 << _queue))
+
+#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
+ _reg |= 1 << _queue; \
+} while (0)
+
+#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
+ _reg &= ~(1 << _queue); \
+} while (0)
+
+/*
+ * Unaligned little endian access
+ */
+#define AR5K_LE_READ_2 ath5k_hw_read_unaligned_16
+#define AR5K_LE_READ_4 ath5k_hw_read_unaligned_32
+#define AR5K_LE_WRITE_2 ath5k_hw_write_unaligned_16
+#define AR5K_LE_WRITE_4 ath5k_hw_write_unaligned_32
+
+#define AR5K_LOW_ID(_a)( \
+(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
+)
+
+#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
+
+/*
+ * Initial register values
+ */
+
+/*
+ * Common initial register values
+ */
+#define AR5K_INIT_MODE CHANNEL_B
+
+#define AR5K_INIT_TX_LATENCY 502
+#define AR5K_INIT_USEC 39
+#define AR5K_INIT_USEC_TURBO 79
+#define AR5K_INIT_USEC_32 31
+#define AR5K_INIT_CARR_SENSE_EN 1
+#define AR5K_INIT_PROG_IFS 920
+#define AR5K_INIT_PROG_IFS_TURBO 960
+#define AR5K_INIT_EIFS 3440
+#define AR5K_INIT_EIFS_TURBO 6880
+#define AR5K_INIT_SLOT_TIME 396
+#define AR5K_INIT_SLOT_TIME_TURBO 480
+#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
+#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
+#define AR5K_INIT_SIFS 560
+#define AR5K_INIT_SIFS_TURBO 480
+#define AR5K_INIT_SH_RETRY 10
+#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
+#define AR5K_INIT_SSH_RETRY 32
+#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
+#define AR5K_INIT_TX_RETRY 10
+#define AR5K_INIT_TOPS 8
+#define AR5K_INIT_RXNOFRM 8
+#define AR5K_INIT_RPGTO 0
+#define AR5K_INIT_TXNOFRM 0
+#define AR5K_INIT_BEACON_PERIOD 65535
+#define AR5K_INIT_TIM_OFFSET 0
+#define AR5K_INIT_BEACON_EN 0
+#define AR5K_INIT_RESET_TSF 0
+
+#define AR5K_INIT_TRANSMIT_LATENCY ( \
+ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
+ (AR5K_INIT_USEC) \
+)
+#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
+ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
+ (AR5K_INIT_USEC_TURBO) \
+)
+#define AR5K_INIT_PROTO_TIME_CNTRL ( \
+ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
+ (AR5K_INIT_PROG_IFS) \
+)
+#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
+ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\
+ (AR5K_INIT_PROG_IFS_TURBO) \
+)
+#define AR5K_INIT_BEACON_CONTROL ( \
+ (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \
+ (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \
+)
+
+/*
+ * Non - common initial register values
+ */
+struct ath5k_ini {
+ u_int16_t ini_register;
+ u_int32_t ini_value;
+
+ enum {
+ AR5K_INI_WRITE = 0,
+ AR5K_INI_READ = 1,
+ } ini_mode;
+};
+
+#define AR5K_INI_VAL_11A 0
+#define AR5K_INI_VAL_11A_TURBO 1
+#define AR5K_INI_VAL_11B 2
+#define AR5K_INI_VAL_11G 3
+#define AR5K_INI_VAL_11G_TURBO 4
+#define AR5K_INI_VAL_XR 0
+#define AR5K_INI_VAL_MAX 5
+
+#define AR5K_INI_PHY_5111 0
+#define AR5K_INI_PHY_5112 1
+#define AR5K_INI_PHY_511X 1
+
+#define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
+#define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
+
+struct ath5k_ini_rf {
+ u_int8_t rf_bank;
+ u_int16_t rf_register;
+ u_int32_t rf_value[5];
+};
+
+#define AR5K_AR5111_INI_RF {
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 0, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
\
+ { 0, 0x989c,
\
+ { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
\
+ { 0, 0x98d4,
\
+ { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
\
+ { 1, 0x98d4,
\
+ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
\
+ { 2, 0x98d4,
\
+ { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
\
+ { 3, 0x98d8,
\
+ { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
\
+ { 6, 0x989c,
\
+ { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
\
+ { 6, 0x989c,
\
+ { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
\
+ { 6, 0x989c,
\
+ { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
\
+ { 6, 0x989c,
\
+ { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
\
+ { 6, 0x989c,
\
+ { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
\
+ { 6, 0x98d4,
\
+ { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
\
+ { 7, 0x989c,
\
+ { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
\
+ { 7, 0x989c,
\
+ { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
\
+ { 7, 0x989c,
\
+ { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
\
+ { 7, 0x989c,
\
+ { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
\
+ { 7, 0x989c,
\
+ { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
\
+ { 7, 0x989c,
\
+ { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
\
+ { 7, 0x989c,
\
+ { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
\
+ { 7, 0x98cc,
\
+ { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
\
+}
+
+#define AR5K_AR5112_INI_RF {
\
+ { 1, 0x98d4,
\
+ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
\
+ { 2, 0x98d0,
\
+ { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
\
+ { 3, 0x98dc,
\
+ { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
\
+ { 6, 0x989c,
\
+ { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
\
+ { 6, 0x989c,
\
+ { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
\
+ { 6, 0x989c,
\
+ { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
\
+ { 6, 0x989c,
\
+ { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
\
+ { 6, 0x989c,
\
+ { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
\
+ { 6, 0x989c,
\
+ { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
\
+ { 6, 0x989c,
\
+ { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
\
+ { 6, 0x989c,
\
+ { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
\
+ { 6, 0x989c,
\
+ { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
\
+ { 6, 0x989c,
\
+ { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
\
+ { 6, 0x989c,
\
+ { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
\
+ { 6, 0x989c,
\
+ { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
\
+ { 6, 0x989c,
\
+ { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
\
+ { 6, 0x989c,
\
+ { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
\
+ { 6, 0x989c,
\
+ { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
\
+ { 6, 0x989c,
\
+ { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
\
+ { 6, 0x989c,
\
+ { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
\
+ { 6, 0x989c,
\
+ { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
\
+ { 6, 0x989c,
\
+ { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
\
+ { 6, 0x989c,
\
+ { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
\
+ { 6, 0x989c,
\
+ { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
\
+ { 6, 0x989c,
\
+ { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
\
+ { 6, 0x989c,
\
+ { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
\
+ { 6, 0x989c,
\
+ { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
\
+ { 6, 0x989c,
\
+ { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
\
+ { 6, 0x989c,
\
+ { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
\
+ { 6, 0x98d0,
\
+ { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
\
+ { 7, 0x989c,
\
+ { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
\
+ { 7, 0x989c,
\
+ { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
\
+ { 7, 0x989c,
\
+ { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
\
+ { 7, 0x989c,
\
+ { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
\
+ { 7, 0x989c,
\
+ { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
\
+ { 7, 0x989c,
\
+ { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
\
+ { 7, 0x989c,
\
+ { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
\
+ { 7, 0x989c,
\
+ { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
\
+ { 7, 0x989c,
\
+ { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
\
+ { 7, 0x989c,
\
+ { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
\
+ { 7, 0x989c,
\
+ { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
\
+ { 7, 0x989c,
\
+ { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
\
+ { 7, 0x98c4,
\
+ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
\
+ }
+
+#define AR5K_AR5112A_INI_RF {
\
+ { 1, 0x98d4,
\
+ { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
\
+ { 2, 0x98d0,
\
+ { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
\
+ { 3, 0x98dc,
\
+ { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
\
+ { 6, 0x989c,
\
+ { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
\
+ { 6, 0x989c,
\
+ { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
\
+ { 6, 0x989c,
\
+ { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
\
+ { 6, 0x989c,
\
+ { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
\
+ { 6, 0x989c,
\
+ { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
\
+ { 6, 0x989c,
\
+ { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
\
+ { 6, 0x989c,
\
+ { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
\
+ { 6, 0x989c,
\
+ { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
\
+ { 6, 0x989c,
\
+ { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
\
+ { 6, 0x989c,
\
+ { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
\
+ { 6, 0x989c,
\
+ { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
\
+ { 6, 0x989c,
\
+ { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
\
+ { 6, 0x989c,
\
+ { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
\
+ { 6, 0x989c,
\
+ { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
\
+ { 6, 0x989c,
\
+ { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
\
+ { 6, 0x989c,
\
+ { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
\
+ { 6, 0x989c,
\
+ { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
\
+ { 6, 0x989c,
\
+ { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
\
+ { 6, 0x989c,
\
+ { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
\
+ { 6, 0x989c,
\
+ { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
\
+ { 6, 0x989c,
\
+ { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
\
+ { 6, 0x989c,
\
+ { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
\
+ { 6, 0x989c,
\
+ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
\
+ { 6, 0x989c,
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
+ { 6, 0x989c,
\
+ { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
\
+ { 6, 0x989c,
\
+ { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
\
+ { 6, 0x989c,
\
+ { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
\
+ { 6, 0x989c,
\
+ { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
\
+ { 6, 0x989c,
\
+ { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
\
+ { 6, 0x98d8,
\
+ { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
\
+ { 7, 0x989c,
\
+ { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
\
+ { 7, 0x989c,
\
+ { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
\
+ { 7, 0x989c,
\
+ { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
\
+ { 7, 0x989c,
\
+ { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
\
+ { 7, 0x989c,
\
+ { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
\
+ { 7, 0x989c,
\
+ { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
\
+ { 7, 0x989c,
\
+ { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
\
+ { 7, 0x989c,
\
+ { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
\
+ { 7, 0x989c,
\
+ { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
\
+ { 7, 0x989c,
\
+ { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
\
+ { 7, 0x989c,
\
+ { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
\
+ { 7, 0x989c,
\
+ { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
\
+ { 7, 0x98c4,
\
+ { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
\
+}
+
+struct ath5k_ini_rfgain {
+ u_int16_t rfg_register;
+ u_int32_t rfg_value[2][2];
+
+#define AR5K_INI_RFGAIN_5GHZ 0
+#define AR5K_INI_RFGAIN_2GHZ 1
+};
+
+#define AR5K_INI_RFGAIN {
\
+ { 0x9a00, {
\
+ { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } },
\
+ { 0x9a04, {
\
+ { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } },
\
+ { 0x9a08, {
\
+ { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } },
\
+ { 0x9a0c, {
\
+ { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } },
\
+ { 0x9a10, {
\
+ { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } },
\
+ { 0x9a14, {
\
+ { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } },
\
+ { 0x9a18, {
\
+ { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } },
\
+ { 0x9a1c, {
\
+ { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } },
\
+ { 0x9a20, {
\
+ { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } },
\
+ { 0x9a24, {
\
+ { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } },
\
+ { 0x9a28, {
\
+ { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } },
\
+ { 0x9a2c, {
\
+ { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } },
\
+ { 0x9a30, {
\
+ { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } },
\
+ { 0x9a34, {
\
+ { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } },
\
+ { 0x9a38, {
\
+ { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } },
\
+ { 0x9a3c, {
\
+ { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } },
\
+ { 0x9a40, {
\
+ { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } },
\
+ { 0x9a44, {
\
+ { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } },
\
+ { 0x9a48, {
\
+ { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } },
\
+ { 0x9a4c, {
\
+ { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } },
\
+ { 0x9a50, {
\
+ { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } },
\
+ { 0x9a54, {
\
+ { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } },
\
+ { 0x9a58, {
\
+ { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } },
\
+ { 0x9a5c, {
\
+ { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } },
\
+ { 0x9a60, {
\
+ { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } },
\
+ { 0x9a64, {
\
+ { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } },
\
+ { 0x9a68, {
\
+ { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } },
\
+ { 0x9a6c, {
\
+ { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } },
\
+ { 0x9a70, {
\
+ { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } },
\
+ { 0x9a74, {
\
+ { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } },
\
+ { 0x9a78, {
\
+ { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } },
\
+ { 0x9a7c, {
\
+ { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } },
\
+ { 0x9a80, {
\
+ { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } },
\
+ { 0x9a84, {
\
+ { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } },
\
+ { 0x9a88, {
\
+ { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } },
\
+ { 0x9a8c, {
\
+ { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } },
\
+ { 0x9a90, {
\
+ { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } },
\
+ { 0x9a94, {
\
+ { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } },
\
+ { 0x9a98, {
\
+ { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } },
\
+ { 0x9a9c, {
\
+ { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } },
\
+ { 0x9aa0, {
\
+ { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } },
\
+ { 0x9aa4, {
\
+ { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } },
\
+ { 0x9aa8, {
\
+ { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } },
\
+ { 0x9aac, {
\
+ { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } },
\
+ { 0x9ab0, {
\
+ { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } },
\
+ { 0x9ab4, {
\
+ { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } },
\
+ { 0x9ab8, {
\
+ { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } },
\
+ { 0x9abc, {
\
+ { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } },
\
+ { 0x9ac0, {
\
+ { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } },
\
+ { 0x9ac4, {
\
+ { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } },
\
+ { 0x9ac8, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } },
\
+ { 0x9acc, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } },
\
+ { 0x9ad0, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } },
\
+ { 0x9ad4, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } },
\
+ { 0x9ad8, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9adc, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9ae0, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9ae4, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9ae8, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9aec, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9af0, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9af4, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9af8, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+ { 0x9afc, {
\
+ { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } },
\
+}
+
+#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00
+#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20
+#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40
+#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60
+#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80
+#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0
+#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0
+#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
+
+/*
+ * Initial register values which have to be loaded into the
+ * card at boot time and after each reset.
+ */
+
+#define AR5K_AR5211_INI { \
+ { 0x000c, 0x00000000 }, \
+ { 0x0028, 0x84849c9c }, \
+ { 0x002c, 0x7c7c7c7c }, \
+ { 0x0034, 0x00000005 }, \
+ { 0x0040, 0x00000000 }, \
+ { 0x0044, 0x00000008 }, \
+ { 0x0048, 0x00000008 }, \
+ { 0x004c, 0x00000010 }, \
+ { 0x0050, 0x00000000 }, \
+ { 0x0054, 0x0000001f }, \
+ { 0x0800, 0x00000000 }, \
+ { 0x0804, 0x00000000 }, \
+ { 0x0808, 0x00000000 }, \
+ { 0x080c, 0x00000000 }, \
+ { 0x0810, 0x00000000 }, \
+ { 0x0814, 0x00000000 }, \
+ { 0x0818, 0x00000000 }, \
+ { 0x081c, 0x00000000 }, \
+ { 0x0820, 0x00000000 }, \
+ { 0x0824, 0x00000000 }, \
+ { 0x1230, 0x00000000 }, \
+ { 0x8004, 0x00000000 }, \
+ { 0x8008, 0x00000000 }, \
+ { 0x800c, 0x00000000 }, \
+ { 0x8018, 0x00000000 }, \
+ { 0x8024, 0x00000000 }, \
+ { 0x8028, 0x00000030 }, \
+ { 0x802c, 0x0007ffff }, \
+ { 0x8030, 0x01ffffff }, \
+ { 0x8034, 0x00000031 }, \
+ { 0x8038, 0x00000000 }, \
+ { 0x803c, 0x00000000 }, \
+ { 0x8040, 0x00000000 }, \
+ { 0x8044, 0x00000002 }, \
+ { 0x8048, 0x00000000 }, \
+ { 0x8054, 0x00000000 }, \
+ { 0x8058, 0x00000000 }, \
+ /* PHY registers */ \
+ { 0x9808, 0x00000000 }, \
+ { 0x980c, 0x2d849093 }, \
+ { 0x9810, 0x7d32e000 }, \
+ { 0x9814, 0x00000f6b }, \
+ { 0x981c, 0x00000000 }, \
+ { 0x982c, 0x00026ffe }, \
+ { 0x9830, 0x00000000 }, \
+ { 0x983c, 0x00020100 }, \
+ { 0x9840, 0x206a017a }, \
+ { 0x984c, 0x1284613c }, \
+ { 0x9854, 0x00000859 }, \
+ { 0x9868, 0x409a4190 }, \
+ { 0x986c, 0x050cb081 }, \
+ { 0x9870, 0x0000000f }, \
+ { 0x9874, 0x00000080 }, \
+ { 0x9878, 0x0000000c }, \
+ { 0x9900, 0x00000000 }, \
+ { 0x9904, 0x00000000 }, \
+ { 0x9908, 0x00000000 }, \
+ { 0x990c, 0x00800000 }, \
+ { 0x9910, 0x00000001 }, \
+ { 0x991c, 0x0000092a }, \
+ { 0x9920, 0x00000000 }, \
+ { 0x9924, 0x00058a05 }, \
+ { 0x9928, 0x00000001 }, \
+ { 0x992c, 0x00000000 }, \
+ { 0x9930, 0x00000000 }, \
+ { 0x9934, 0x00000000 }, \
+ { 0x9938, 0x00000000 }, \
+ { 0x993c, 0x0000003f }, \
+ { 0x9940, 0x00000004 }, \
+ { 0x9948, 0x00000000 }, \
+ { 0x994c, 0x00000000 }, \
+ { 0x9950, 0x00000000 }, \
+ { 0x9954, 0x5d50f14c }, \
+ { 0x9958, 0x00000018 }, \
+ { 0x995c, 0x004b6a8e }, \
+ { 0xa184, 0x06ff05ff }, \
+ { 0xa188, 0x07ff07ff }, \
+ { 0xa18c, 0x08ff08ff }, \
+ { 0xa190, 0x09ff09ff }, \
+ { 0xa194, 0x0aff0aff }, \
+ { 0xa198, 0x0bff0bff }, \
+ { 0xa19c, 0x0cff0cff }, \
+ { 0xa1a0, 0x0dff0dff }, \
+ { 0xa1a4, 0x0fff0eff }, \
+ { 0xa1a8, 0x12ff12ff }, \
+ { 0xa1ac, 0x14ff13ff }, \
+ { 0xa1b0, 0x16ff15ff }, \
+ { 0xa1b4, 0x19ff17ff }, \
+ { 0xa1b8, 0x1bff1aff }, \
+ { 0xa1bc, 0x1eff1dff }, \
+ { 0xa1c0, 0x23ff20ff }, \
+ { 0xa1c4, 0x27ff25ff }, \
+ { 0xa1c8, 0x2cff29ff }, \
+ { 0xa1cc, 0x31ff2fff }, \
+ { 0xa1d0, 0x37ff34ff }, \
+ { 0xa1d4, 0x3aff3aff }, \
+ { 0xa1d8, 0x3aff3aff }, \
+ { 0xa1dc, 0x3aff3aff }, \
+ { 0xa1e0, 0x3aff3aff }, \
+ { 0xa1e4, 0x3aff3aff }, \
+ { 0xa1e8, 0x3aff3aff }, \
+ { 0xa1ec, 0x3aff3aff }, \
+ { 0xa1f0, 0x3aff3aff }, \
+ { 0xa1f4, 0x3aff3aff }, \
+ { 0xa1f8, 0x3aff3aff }, \
+ { 0xa1fc, 0x3aff3aff }, \
+ /* BB gain table (64bytes) */ \
+ { 0x9b00, 0x00000000 }, \
+ { 0x9b04, 0x00000020 }, \
+ { 0x9b08, 0x00000010 }, \
+ { 0x9b0c, 0x00000030 }, \
+ { 0x9b10, 0x00000008 }, \
+ { 0x9b14, 0x00000028 }, \
+ { 0x9b18, 0x00000004 }, \
+ { 0x9b1c, 0x00000024 }, \
+ { 0x9b20, 0x00000014 }, \
+ { 0x9b24, 0x00000034 }, \
+ { 0x9b28, 0x0000000c }, \
+ { 0x9b2c, 0x0000002c }, \
+ { 0x9b30, 0x00000002 }, \
+ { 0x9b34, 0x00000022 }, \
+ { 0x9b38, 0x00000012 }, \
+ { 0x9b3c, 0x00000032 }, \
+ { 0x9b40, 0x0000000a }, \
+ { 0x9b44, 0x0000002a }, \
+ { 0x9b48, 0x00000006 }, \
+ { 0x9b4c, 0x00000026 }, \
+ { 0x9b50, 0x00000016 }, \
+ { 0x9b54, 0x00000036 }, \
+ { 0x9b58, 0x0000000e }, \
+ { 0x9b5c, 0x0000002e }, \
+ { 0x9b60, 0x00000001 }, \
+ { 0x9b64, 0x00000021 }, \
+ { 0x9b68, 0x00000011 }, \
+ { 0x9b6c, 0x00000031 }, \
+ { 0x9b70, 0x00000009 }, \
+ { 0x9b74, 0x00000029 }, \
+ { 0x9b78, 0x00000005 }, \
+ { 0x9b7c, 0x00000025 }, \
+ { 0x9b80, 0x00000015 }, \
+ { 0x9b84, 0x00000035 }, \
+ { 0x9b88, 0x0000000d }, \
+ { 0x9b8c, 0x0000002d }, \
+ { 0x9b90, 0x00000003 }, \
+ { 0x9b94, 0x00000023 }, \
+ { 0x9b98, 0x00000013 }, \
+ { 0x9b9c, 0x00000033 }, \
+ { 0x9ba0, 0x0000000b }, \
+ { 0x9ba4, 0x0000002b }, \
+ { 0x9ba8, 0x0000002b }, \
+ { 0x9bac, 0x0000002b }, \
+ { 0x9bb0, 0x0000002b }, \
+ { 0x9bb4, 0x0000002b }, \
+ { 0x9bb8, 0x0000002b }, \
+ { 0x9bbc, 0x0000002b }, \
+ { 0x9bc0, 0x0000002b }, \
+ { 0x9bc4, 0x0000002b }, \
+ { 0x9bc8, 0x0000002b }, \
+ { 0x9bcc, 0x0000002b }, \
+ { 0x9bd0, 0x0000002b }, \
+ { 0x9bd4, 0x0000002b }, \
+ { 0x9bd8, 0x0000002b }, \
+ { 0x9bdc, 0x0000002b }, \
+ { 0x9be0, 0x0000002b }, \
+ { 0x9be4, 0x0000002b }, \
+ { 0x9be8, 0x0000002b }, \
+ { 0x9bec, 0x0000002b }, \
+ { 0x9bf0, 0x0000002b }, \
+ { 0x9bf4, 0x0000002b }, \
+ { 0x9bf8, 0x00000002 }, \
+ { 0x9bfc, 0x00000016 }, \
+ /* PHY activation */ \
+ { 0x98d4, 0x00000020 }, \
+ { 0x98d8, 0x00601068 }, \
+}
+
+struct ath5k_ar5212_ini {
+ u_int8_t ini_flags;
+ u_int16_t ini_register;
+ u_int32_t ini_value;
+
+#define AR5K_INI_FLAG_511X 0x00
+#define AR5K_INI_FLAG_5111 0x01
+#define AR5K_INI_FLAG_5112 0x02
+#define AR5K_INI_FLAG_BOTH (AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112)
+};
+
+#define AR5K_AR5212_INI { \
+ { AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 }, \
+ { AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f }, \
+ { AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x081c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0820, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x0824, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1230, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1270, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1038, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1078, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x10b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x10f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1138, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1178, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x11b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x11f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1238, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1278, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x12b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x12f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1338, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1378, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x13b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x13f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1438, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1478, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x14b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x14f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1538, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1578, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x15b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x15f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1638, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1678, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x16b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x16f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1738, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x1778, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x17b8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x17f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x103c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x107c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x10bc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x10fc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x113c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x117c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x11bc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x11fc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x123c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x127c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x12bc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x12fc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x133c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x137c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x13bc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x13fc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x143c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x147c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8004, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8008, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x800c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8018, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8020, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8024, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8028, 0x00000030 }, \
+ { AR5K_INI_FLAG_BOTH, 0x802c, 0x0007ffff }, \
+ { AR5K_INI_FLAG_BOTH, 0x8030, 0x01ffffff }, \
+ { AR5K_INI_FLAG_BOTH, 0x8034, 0x00000031 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8038, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x803c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8048, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8054, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8058, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x805c, 0xffffc7ff }, \
+ { AR5K_INI_FLAG_BOTH, 0x8080, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8084, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8088, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x808c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8090, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8094, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8098, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80c0, 0x2a82301a }, \
+ { AR5K_INI_FLAG_BOTH, 0x80c4, 0x05dc01e0 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80c8, 0x1f402710 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80cc, 0x01f40000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80d0, 0x00001e1c }, \
+ { AR5K_INI_FLAG_BOTH, 0x80d4, 0x0002aaaa }, \
+ { AR5K_INI_FLAG_BOTH, 0x80d8, 0x02005555 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80dc, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80e0, 0xffffffff }, \
+ { AR5K_INI_FLAG_BOTH, 0x80e4, 0x0000ffff }, \
+ { AR5K_INI_FLAG_BOTH, 0x80e8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80ec, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80f0, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80f4, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80f8, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x80fc, 0x00000088 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8700, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8704, 0x0000008c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8708, 0x000000e4 }, \
+ { AR5K_INI_FLAG_BOTH, 0x870c, 0x000002d5 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8710, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8714, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8718, 0x000000a0 }, \
+ { AR5K_INI_FLAG_BOTH, 0x871c, 0x000001c9 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8720, 0x0000002c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8724, 0x0000002c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8728, 0x00000030 }, \
+ { AR5K_INI_FLAG_BOTH, 0x872c, 0x0000003c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8730, 0x0000002c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8734, 0x0000002c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8738, 0x00000030 }, \
+ { AR5K_INI_FLAG_BOTH, 0x873c, 0x0000003c }, \
+ { AR5K_INI_FLAG_BOTH, 0x8740, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8744, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8748, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x874c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8750, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8754, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8758, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x875c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8760, 0x000000d5 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8764, 0x000000df }, \
+ { AR5K_INI_FLAG_BOTH, 0x8768, 0x00000102 }, \
+ { AR5K_INI_FLAG_BOTH, 0x876c, 0x0000013a }, \
+ { AR5K_INI_FLAG_BOTH, 0x8770, 0x00000075 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8774, 0x0000007f }, \
+ { AR5K_INI_FLAG_BOTH, 0x8778, 0x000000a2 }, \
+ { AR5K_INI_FLAG_BOTH, 0x877c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8100, 0x00010002 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8104, 0x00000001 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8108, 0x000000c0 }, \
+ { AR5K_INI_FLAG_BOTH, 0x810c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8110, 0x00000168 }, \
+ { AR5K_INI_FLAG_BOTH, 0x8114, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87c0, 0x03020100 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87c4, 0x07060504 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87c8, 0x0b0a0908 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87cc, 0x0f0e0d0c }, \
+ { AR5K_INI_FLAG_BOTH, 0x87d0, 0x13121110 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87d4, 0x17161514 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87d8, 0x1b1a1918 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87dc, 0x1f1e1d1c }, \
+ { AR5K_INI_FLAG_BOTH, 0x87e0, 0x03020100 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87e4, 0x07060504 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87e8, 0x0b0a0908 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87ec, 0x0f0e0d0c }, \
+ { AR5K_INI_FLAG_BOTH, 0x87f0, 0x13121110 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87f4, 0x17161514 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87f8, 0x1b1a1918 }, \
+ { AR5K_INI_FLAG_BOTH, 0x87fc, 0x1f1e1d1c }, \
+ /* PHY registers */ \
+ { AR5K_INI_FLAG_BOTH, 0x9808, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x980c, 0xad848e19 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9810, 0x7d28e000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9814, 0x9c0a9f6b }, \
+ { AR5K_INI_FLAG_BOTH, 0x981c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x982c, 0x00022ffe }, \
+ { AR5K_INI_FLAG_BOTH, 0x983c, 0x00020100 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9840, 0x206a017a }, \
+ { AR5K_INI_FLAG_BOTH, 0x984c, 0x1284613c }, \
+ { AR5K_INI_FLAG_BOTH, 0x9854, 0x00000859 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9900, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9904, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 }, \
+ { AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a }, \
+ { AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 }, \
+ { AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9934, 0x1e1f2022 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9938, 0x0a0b0c0d }, \
+ { AR5K_INI_FLAG_BOTH, 0x993c, 0x0000003f }, \
+ { AR5K_INI_FLAG_BOTH, 0x9940, 0x00000004 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9948, 0x9280b212 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9954, 0x5d50e188 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9958, 0x000000ff }, \
+ { AR5K_INI_FLAG_BOTH, 0x995c, 0x004b6a8e }, \
+ { AR5K_INI_FLAG_BOTH, 0x9968, 0x000003ce }, \
+ { AR5K_INI_FLAG_BOTH, 0x9970, 0x192fb515 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9974, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9978, 0x00000001 }, \
+ { AR5K_INI_FLAG_BOTH, 0x997c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa184, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa188, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa18c, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa190, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa194, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa198, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa19c, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1a0, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1a4, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1a8, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1ac, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1b0, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1b4, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1b8, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1bc, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1c0, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1c4, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1c8, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1cc, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1d0, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1d4, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1d8, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1dc, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1e0, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1e4, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1e8, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1ec, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1f0, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff }, \
+ { AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a }, \
+ { AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa234, 0x20202020 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa238, 0x20202020 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa23c, 0x13c889af }, \
+ { AR5K_INI_FLAG_BOTH, 0xa240, 0x38490a20 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa244, 0x00007bb6 }, \
+ { AR5K_INI_FLAG_BOTH, 0xa248, 0x0fff3ffc }, \
+ { AR5K_INI_FLAG_BOTH, 0x9b00, 0x00000000 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9b28, 0x0000000c }, \
+ { AR5K_INI_FLAG_BOTH, 0x9b38, 0x00000012 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9b64, 0x00000021 }, \
+ { AR5K_INI_FLAG_BOTH, 0x9b8c, 0x0000002d }, \
+ { AR5K_INI_FLAG_BOTH, 0x9b9c, 0x00000033 }, \
+ /* AR5111 specific */ \
+ { AR5K_INI_FLAG_5111, 0x9930, 0x00004883 }, \
+ { AR5K_INI_FLAG_5111, 0xa204, 0x00000000 }, \
+ { AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 }, \
+ { AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a }, \
+ { AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 }, \
+ { AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 }, \
+ { AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 }, \
+ { AR5K_INI_FLAG_5111, 0x9b10, 0x00000008 }, \
+ { AR5K_INI_FLAG_5111, 0x9b14, 0x00000028 }, \
+ { AR5K_INI_FLAG_5111, 0x9b18, 0x00000004 }, \
+ { AR5K_INI_FLAG_5111, 0x9b1c, 0x00000024 }, \
+ { AR5K_INI_FLAG_5111, 0x9b20, 0x00000014 }, \
+ { AR5K_INI_FLAG_5111, 0x9b24, 0x00000034 }, \
+ { AR5K_INI_FLAG_5111, 0x9b2c, 0x0000002c }, \
+ { AR5K_INI_FLAG_5111, 0x9b30, 0x00000002 }, \
+ { AR5K_INI_FLAG_5111, 0x9b34, 0x00000022 }, \
+ { AR5K_INI_FLAG_5111, 0x9b3c, 0x00000032 }, \
+ { AR5K_INI_FLAG_5111, 0x9b40, 0x0000000a }, \
+ { AR5K_INI_FLAG_5111, 0x9b44, 0x0000002a }, \
+ { AR5K_INI_FLAG_5111, 0x9b48, 0x00000006 }, \
+ { AR5K_INI_FLAG_5111, 0x9b4c, 0x00000026 }, \
+ { AR5K_INI_FLAG_5111, 0x9b50, 0x00000016 }, \
+ { AR5K_INI_FLAG_5111, 0x9b54, 0x00000036 }, \
+ { AR5K_INI_FLAG_5111, 0x9b58, 0x0000000e }, \
+ { AR5K_INI_FLAG_5111, 0x9b5c, 0x0000002e }, \
+ { AR5K_INI_FLAG_5111, 0x9b60, 0x00000001 }, \
+ { AR5K_INI_FLAG_5111, 0x9b68, 0x00000011 }, \
+ { AR5K_INI_FLAG_5111, 0x9b6c, 0x00000031 }, \
+ { AR5K_INI_FLAG_5111, 0x9b70, 0x00000009 }, \
+ { AR5K_INI_FLAG_5111, 0x9b74, 0x00000029 }, \
+ { AR5K_INI_FLAG_5111, 0x9b78, 0x00000005 }, \
+ { AR5K_INI_FLAG_5111, 0x9b7c, 0x00000025 }, \
+ { AR5K_INI_FLAG_5111, 0x9b80, 0x00000015 }, \
+ { AR5K_INI_FLAG_5111, 0x9b84, 0x00000035 }, \
+ { AR5K_INI_FLAG_5111, 0x9b88, 0x0000000d }, \
+ { AR5K_INI_FLAG_5111, 0x9b90, 0x00000003 }, \
+ { AR5K_INI_FLAG_5111, 0x9b94, 0x00000023 }, \
+ { AR5K_INI_FLAG_5111, 0x9b98, 0x00000013 }, \
+ { AR5K_INI_FLAG_5111, 0x9ba0, 0x0000000b }, \
+ { AR5K_INI_FLAG_5111, 0x9ba4, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9ba8, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bac, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bb0, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bb4, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bb8, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bbc, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bc0, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bc4, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bc8, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bcc, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bd0, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bd4, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bd8, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bdc, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9be0, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9be4, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9be8, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bec, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bf0, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bf4, 0x0000002b }, \
+ { AR5K_INI_FLAG_5111, 0x9bf8, 0x00000002 }, \
+ { AR5K_INI_FLAG_5111, 0x9bfc, 0x00000016 }, \
+ /* AR5112 specific */ \
+ { AR5K_INI_FLAG_5112, 0x9930, 0x00004882 }, \
+ { AR5K_INI_FLAG_5112, 0x9b04, 0x00000001 }, \
+ { AR5K_INI_FLAG_5112, 0x9b08, 0x00000002 }, \
+ { AR5K_INI_FLAG_5112, 0x9b0c, 0x00000003 }, \
+ { AR5K_INI_FLAG_5112, 0x9b10, 0x00000004 }, \
+ { AR5K_INI_FLAG_5112, 0x9b14, 0x00000005 }, \
+ { AR5K_INI_FLAG_5112, 0x9b18, 0x00000008 }, \
+ { AR5K_INI_FLAG_5112, 0x9b1c, 0x00000009 }, \
+ { AR5K_INI_FLAG_5112, 0x9b20, 0x0000000a }, \
+ { AR5K_INI_FLAG_5112, 0x9b24, 0x0000000b }, \
+ { AR5K_INI_FLAG_5112, 0x9b2c, 0x0000000d }, \
+ { AR5K_INI_FLAG_5112, 0x9b30, 0x00000010 }, \
+ { AR5K_INI_FLAG_5112, 0x9b34, 0x00000011 }, \
+ { AR5K_INI_FLAG_5112, 0x9b3c, 0x00000013 }, \
+ { AR5K_INI_FLAG_5112, 0x9b40, 0x00000014 }, \
+ { AR5K_INI_FLAG_5112, 0x9b44, 0x00000015 }, \
+ { AR5K_INI_FLAG_5112, 0x9b48, 0x00000018 }, \
+ { AR5K_INI_FLAG_5112, 0x9b4c, 0x00000019 }, \
+ { AR5K_INI_FLAG_5112, 0x9b50, 0x0000001a }, \
+ { AR5K_INI_FLAG_5112, 0x9b54, 0x0000001b }, \
+ { AR5K_INI_FLAG_5112, 0x9b58, 0x0000001c }, \
+ { AR5K_INI_FLAG_5112, 0x9b5c, 0x0000001d }, \
+ { AR5K_INI_FLAG_5112, 0x9b60, 0x00000020 }, \
+ { AR5K_INI_FLAG_5112, 0x9b68, 0x00000022 }, \
+ { AR5K_INI_FLAG_5112, 0x9b6c, 0x00000023 }, \
+ { AR5K_INI_FLAG_5112, 0x9b70, 0x00000024 }, \
+ { AR5K_INI_FLAG_5112, 0x9b74, 0x00000025 }, \
+ { AR5K_INI_FLAG_5112, 0x9b78, 0x00000028 }, \
+ { AR5K_INI_FLAG_5112, 0x9b7c, 0x00000029 }, \
+ { AR5K_INI_FLAG_5112, 0x9b80, 0x0000002a }, \
+ { AR5K_INI_FLAG_5112, 0x9b84, 0x0000002b }, \
+ { AR5K_INI_FLAG_5112, 0x9b88, 0x0000002c }, \
+ { AR5K_INI_FLAG_5112, 0x9b90, 0x00000030 }, \
+ { AR5K_INI_FLAG_5112, 0x9b94, 0x00000031 }, \
+ { AR5K_INI_FLAG_5112, 0x9b98, 0x00000032 }, \
+ { AR5K_INI_FLAG_5112, 0x9ba0, 0x00000034 }, \
+ { AR5K_INI_FLAG_5112, 0x9ba4, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9ba8, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bac, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bb0, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bb4, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bb8, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bbc, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bc0, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bc4, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bc8, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bcc, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bd0, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bd4, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bd8, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bdc, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9be0, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9be4, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9be8, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bec, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bf0, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bf4, 0x00000035 }, \
+ { AR5K_INI_FLAG_5112, 0x9bf8, 0x00000010 }, \
+ { AR5K_INI_FLAG_5112, 0x9bfc, 0x0000001a }, \
+}
+
+struct ath5k_ar5211_ini_mode {
+ u_int16_t mode_register;
+ u_int32_t mode_value[4];
+};
+
+#define AR5K_AR5211_INI_MODE { \
+ { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \
+ { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
+ { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \
+ { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \
+ { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \
+ { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \
+ { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \
+ { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \
+ { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \
+ { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \
+ { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \
+ { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \
+ { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \
+ { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \
+ { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \
+ { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \
+ { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \
+ { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \
+ { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \
+ { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \
+ { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \
+ { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \
+ { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \
+ { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \
+ { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \
+ { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \
+}
+
+struct ath5k_ar5212_ini_mode {
+ u_int16_t mode_register;
+ u_int8_t mode_flags;
+ u_int32_t mode_value[2][5];
+};
+
+#define AR5K_AR5212_INI_MODE {
\
+ { 0x0030, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 }
\
+ } },
\
+ { 0x1040, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1044, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1048, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x104c, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1050, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1054, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1058, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x105c, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1060, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1064, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f }
\
+ } },
\
+ { 0x1030, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 }
\
+ } },
\
+ { 0x1070, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 }
\
+ } },
\
+ { 0x10b0, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 }
\
+ } },
\
+ { 0x10f0, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 }
\
+ } },
\
+ { 0x8014, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 }
\
+ } },
\
+ { 0x9804, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 }
\
+ } },
\
+ { 0x9820, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 }
\
+ } },
\
+ { 0x9834, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }
\
+ } },
\
+ { 0x9838, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b }
\
+ } },
\
+ { 0x9844, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x1372161c, 0x13721c25, 0x13721728, 0x137216a2, 0x13721c25 }
\
+ } },
\
+ { 0x9850, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 }
\
+ } },
\
+ { 0x9858, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e }
\
+ } },
\
+ { 0x9860, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 }
\
+ } },
\
+ { 0x9864, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }
\
+ } },
\
+ { 0x9868, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 }
\
+ } },
\
+ { 0x9918, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 }
\
+ } },
\
+ { 0x9924, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 }
\
+ } },
\
+ { 0xa180, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x10ff14ff, 0x10ff14ff, 0x10ff10ff, 0x10ff19ff, 0x10ff19ff }
\
+ } },
\
+ { 0xa230, AR5K_INI_FLAG_511X, {
\
+ { 0, },
\
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 }
\
+ } },
\
+ { 0x801c, AR5K_INI_FLAG_BOTH, {
\
+ { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x128d8fab, 0x09880fcf },
\
+ { 0x128d93a7, 0x098813cf, 0x04e01395, 0x128d93ab, 0x098813cf }
\
+ } },
\
+ { 0x9824, AR5K_INI_FLAG_BOTH, {
\
+ { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e },
\
+ { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }
\
+ } },
\
+ { 0x9828, AR5K_INI_FLAG_BOTH, {
\
+ { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 },
\
+ { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 }
\
+ } },
\
+ { 0x9848, AR5K_INI_FLAG_BOTH, {
\
+ { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 },
\
+ { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 }
\
+ } },
\
+ { 0x985c, AR5K_INI_FLAG_BOTH, {
\
+ { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e },
\
+ { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e }
\
+ } },
\
+ { 0x986c, AR5K_INI_FLAG_BOTH, {
\
+ { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 },
\
+ { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }
\
+ } },
\
+ { 0x9914, AR5K_INI_FLAG_BOTH, {
\
+ { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 },
\
+ { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 }
\
+ } },
\
+ { 0x9944, AR5K_INI_FLAG_BOTH, {
\
+ { 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 },
\
+ { 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 }
\
+ } },
\
+ { 0xa204, AR5K_INI_FLAG_5112, {
\
+ { 0, },
\
+ { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 }
\
+ } },
\
+ { 0xa208, AR5K_INI_FLAG_5112, {
\
+ { 0, },
\
+ { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 }
\
+ } },
\
+ { 0xa20c, AR5K_INI_FLAG_5112, {
\
+ { 0, },
\
+ { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 }
\
+ } },
\
+}
+
+struct ath5k_ar5211_ini_rf {
+ u_int16_t rf_register;
+ u_int32_t rf_value[2];
+};
+
+#define AR5K_AR5211_INI_RF { \
+ { 0x0000a204, { 0x00000000, 0x00000000 } }, \
+ { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \
+ { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \
+ { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \
+ { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \
+ { 0x0000a218, { 0x13800040, 0x13800040 } }, \
+ { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \
+ { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \
+ { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \
+ { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \
+ { 0x0000a22c, { 0x00000020, 0x00000020 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00380000, 0x00380000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \
+ { 0x000098d4, { 0x00000000, 0x00000004 } }, \
+ \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x10000000, 0x10000000 } }, \
+ { 0x0000989c, { 0x04000000, 0x04000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x00000000 } }, \
+ { 0x0000989c, { 0x00000000, 0x0a000000 } }, \
+ { 0x0000989c, { 0x00380080, 0x02380080 } }, \
+ { 0x0000989c, { 0x00020006, 0x00000006 } }, \
+ { 0x0000989c, { 0x00000092, 0x00000092 } }, \
+ { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \
+ { 0x0000989c, { 0x00040007, 0x00040007 } }, \
+ { 0x000098d4, { 0x0000001a, 0x0000001a } }, \
+ { 0x0000989c, { 0x00000048, 0x00000048 } }, \
+ { 0x0000989c, { 0x00000010, 0x00000010 } }, \
+ { 0x0000989c, { 0x00000008, 0x00000008 } }, \
+ { 0x0000989c, { 0x0000000f, 0x0000000f } }, \
+ { 0x0000989c, { 0x000000f2, 0x00000062 } }, \
+ { 0x0000989c, { 0x0000904f, 0x0000904c } }, \
+ { 0x0000989c, { 0x0000125a, 0x0000129a } }, \
+ { 0x000098cc, { 0x0000000e, 0x0000000f } }, \
+}
+
+
+
+
+/*
+ * Internal RX/TX descriptor structures
+ * (rX: reserved fields possibily used by future versions of the ar5k chipset)
+ */
+
+struct ath5k_rx_desc {
+ /*
+ * RX control word 0
+ */
+ u_int32_t rx_control_0;
+
+#define AR5K_DESC_RX_CTL0 0x00000000
+
+ /*
+ * RX control word 1
+ */
+ u_int32_t rx_control_1;
+
+#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff
+#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000
+} __attribute__((packed));
+
+struct ath5k_ar5211_rx_status {
+ /*
+ * RX status word 0
+ */
+ u_int32_t rx_status_0;
+
+#define AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN 0x00000fff
+#define AR5K_AR5211_DESC_RX_STATUS0_MORE 0x00001000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE_S 15
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x38000000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 27
+
+ /*
+ * RX status word 1
+ */
+ u_int32_t rx_status_1;
+
+#define AR5K_AR5211_DESC_RX_STATUS1_DONE 0x00000001
+#define AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002
+#define AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR 0x00000004
+#define AR5K_AR5211_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008
+#define AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010
+#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR 0x000000e0
+#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR_S 5
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX 0x00007e00
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_S 9
+#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
+#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000
+} __attribute__((packed));
+
+struct ath5k_ar5212_rx_status {
+ /*
+ * RX status word 0
+ */
+ u_int32_t rx_status_0;
+
+#define AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN 0x00000fff
+#define AR5K_AR5212_DESC_RX_STATUS0_MORE 0x00001000
+#define AR5K_AR5212_DESC_RX_STATUS0_DECOMP_CRC_ERROR 0x00002000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE 0x000f8000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE_S 15
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x0ff00000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 20
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA 0xf0000000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 28
+
+ /*
+ * RX status word 1
+ */
+ u_int32_t rx_status_1;
+
+#define AR5K_AR5212_DESC_RX_STATUS1_DONE 0x00000001
+#define AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002
+#define AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR 0x00000004
+#define AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000008
+#define AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR 0x00000010
+#define AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR 0x00000020
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX 0x0000fe00
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_S 9
+#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
+#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 16
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_CACHE_MISS 0x80000000
+} __attribute__((packed));
+
+struct ath5k_ar5212_rx_error {
+ /*
+ * RX error word 0
+ */
+ u_int32_t rx_error_0;
+
+#define AR5K_AR5212_DESC_RX_ERROR0 0x00000000
+
+ /*
+ * RX error word 1
+ */
+ u_int32_t rx_error_1;
+
+#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE 0x0000ff00
+#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE_S 8
+} __attribute__((packed));
+
+#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00
+#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20
+#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40
+#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60
+#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80
+#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0
+#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0
+#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
+
+struct ath5k_ar5211_tx_desc {
+ /*
+ * TX control word 0
+ */
+ u_int32_t tx_control_0;
+
+#define AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN 0x00000fff
+#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE 0x003c0000
+#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE_S 18
+#define AR5K_AR5211_DESC_TX_CTL0_RTSENA 0x00400000
+#define AR5K_AR5211_DESC_TX_CTL0_VEOL 0x00800000
+#define AR5K_AR5211_DESC_TX_CTL0_CLRDMASK 0x01000000
+#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000
+#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT_S 25
+#define AR5K_AR5211_DESC_TX_CTL0_INTREQ 0x20000000
+#define AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000
+
+ /*
+ * TX control word 1
+ */
+ u_int32_t tx_control_1;
+
+#define AR5K_AR5211_DESC_TX_CTL1_BUF_LEN 0x00000fff
+#define AR5K_AR5211_DESC_TX_CTL1_MORE 0x00001000
+#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
+#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13
+#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE 0x00700000
+#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE_S 20
+#define AR5K_AR5211_DESC_TX_CTL1_NOACK 0x00800000
+} __attribute__((packed));
+
+struct ath5k_ar5212_tx_desc {
+ /*
+ * TX control word 0
+ */
+ u_int32_t tx_control_0;
+
+#define AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN 0x00000fff
+#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER 0x003f0000
+#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER_S 16
+#define AR5K_AR5212_DESC_TX_CTL0_RTSENA 0x00400000
+#define AR5K_AR5212_DESC_TX_CTL0_VEOL 0x00800000
+#define AR5K_AR5212_DESC_TX_CTL0_CLRDMASK 0x01000000
+#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000
+#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT_S 25
+#define AR5K_AR5212_DESC_TX_CTL0_INTREQ 0x20000000
+#define AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000
+#define AR5K_AR5212_DESC_TX_CTL0_CTSENA 0x80000000
+
+ /*
+ * TX control word 1
+ */
+ u_int32_t tx_control_1;
+
+#define AR5K_AR5212_DESC_TX_CTL1_BUF_LEN 0x00000fff
+#define AR5K_AR5212_DESC_TX_CTL1_MORE 0x00001000
+#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
+#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13
+#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE 0x00f00000
+#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE_S 20
+#define AR5K_AR5212_DESC_TX_CTL1_NOACK 0x01000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC 0x06000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC_S 25
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN 0x18000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN_S 27
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN 0x60000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN_S 29
+
+ /*
+ * TX control word 2
+ */
+ u_int32_t tx_control_2;
+
+#define AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION 0x00007fff
+#define AR5K_AR5212_DESC_TX_CTL2_DURATION_UPDATE_ENABLE 0x00008000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0 0x000f0000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0_S 16
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1 0x00f00000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1_S 20
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2 0x0f000000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2_S 24
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3 0xf0000000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3_S 28
+
+ /*
+ * TX control word 3
+ */
+ u_int32_t tx_control_3;
+
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0 0x0000001f
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1 0x000003e0
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1_S 5
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2 0x00007c00
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2_S 10
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3 0x000f8000
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3_S 15
+#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE 0x01f00000
+#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE_S 20
+} __attribute__((packed));
+
+struct ath5k_tx_status {
+ /*
+ * TX status word 0
+ */
+ u_int32_t tx_status_0;
+
+#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
+#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
+#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
+#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008
+#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0
+#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4
+#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00
+#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8
+#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000
+#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
+#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
+#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
+
+ /*
+ * TX status word 1
+ */
+ u_int32_t tx_status_1;
+
+#define AR5K_DESC_TX_STATUS1_DONE 0x00000001
+#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
+#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1
+#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
+#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
+#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000
+#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21
+#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000
+#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000
+} __attribute__((packed));
+
diff -Naur qemu/hw/ath5kreg.h qemu-altered/hw/ath5kreg.h
--- qemu/hw/ath5kreg.h 1970-01-01 01:00:00.000000000 +0100
+++ qemu-altered/hw/ath5kreg.h 2008-03-01 13:20:07.000000000 +0100
@@ -0,0 +1,1878 @@
+/*-
+ * Copyright (c) 2007 Nick Kossifidis <address@hidden>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ * redistribution must be conditioned upon including a substantially
+ * similar Disclaimer requirement for further binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ * of any contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+/*
+ * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
+ * maintained by Reyk Floeter
+ *
+ * I tried to document those registers by looking at ar5k code, some
+ * 802.11 (802.11e mostly) papers and by reading various public available
+ * Atheros presentations and papers like these:
+ *
+ * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
+ * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
+ *
+ * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
+ */
+
+
+#define ATH_HW_IRQ_PENDING 0x4008
+#define ATH_HW_IRQ_PENDING_FALSE 0
+#define ATH_HW_IRQ_PENDING_TRUE 1
+
+/*====MAC DMA REGISTERS====*/
+
+/*
+ * AR5210-Specific TXDP registers
+ * 5210 has only 2 transmit queues so no DCU/QCU, just
+ * 2 transmit descriptor pointers...
+ */
+#define AR5K_NOQCU_TXDP0 0x0000 /*Queue 0 - data*/
+#define AR5K_NOQCU_TXDP1 0x0004 /*Queue 1 - beacons*/
+
+/*
+ * Mac Control Register
+ */
+#define AR5K_CR 0x0008 /*Register Address*/
+#define AR5K_CR_TXE0 0x00000001 /*TX Enable for queue 0 on 5210*/
+#define AR5K_CR_TXE1 0x00000002 /*TX Enable for queue 1 on 5210*/
+#define AR5K_CR_RXE 0x00000004 /*RX Enable*/
+#define AR5K_CR_TXD0 0x00000008 /*TX Disable for queue 0 on 5210*/
+#define AR5K_CR_TXD1 0x00000010 /*TX Disable for queue 1 on 5210*/
+#define AR5K_CR_RXD 0x00000020 /*RX Disable*/
+#define AR5K_CR_SWI 0x00000040
+
+/*
+ * RX Descriptor Pointer register
+ */
+#define AR5K_RXDP 0x000c
+
+/*
+ * Configuration and status register
+ */
+#define AR5K_CFG 0x0014 /*Register
Address*/
+#define AR5K_CFG_SWTD 0x00000001 /*Bitswap TX descriptor
(for big endian archs)*/
+#define AR5K_CFG_SWTB 0x00000002 /*Bitswap TX buffer
(?)*/
+#define AR5K_CFG_SWRD 0x00000004 /*Bitswap RX
descriptor*/
+#define AR5K_CFG_SWRB 0x00000008 /*Bitswap RX buffer
(?)*/
+#define AR5K_CFG_SWRG 0x00000010
+#define AR5K_CFG_ADHOC 0x00000020 /*not found on 5210*/
+#define AR5K_CFG_PHY_OK 0x00000100 /*not found on 5210*/
+#define AR5K_CFG_EEBS 0x00000200 /*EEPROM is busy*/
+#define AR5K_CFG_CLKGD 0x00000400
+#define AR5K_CFG_TXCNT 0x00007800 /*5210 only*/
+#define AR5K_CFG_TXCNT_S 11
+#define AR5K_CFG_TXFSTAT 0x00008000 /*5210 only*/
+#define AR5K_CFG_TXFSTRT 0x00010000 /*5210 only*/
+#define AR5K_CFG_PCI_THRES 0x00060000 /*not found on 5210*/
+#define AR5K_CFG_PCI_THRES_S 17
+
+/*
+ * Interrupt enable register
+ */
+#define AR5K_IER 0x0024 /*Register Address*/
+#define AR5K_IER_DISABLE 0x00000000 /*Disable card interrupts*/
+#define AR5K_IER_ENABLE 0x00000001 /*Enable card
interrupts*/
+
+
+/*
+ * 0x0028 is Beacon Control Register on 5210
+ * and first RTS duration register on 5211
+ */
+
+/*
+ * Beacon control register -5210 only-
+ */
+#define AR5K_BCR 0x0028 /*Register Address*/
+#define AR5K_BCR_AP 0x00000000 /*AP mode*/
+#define AR5K_BCR_ADHOC 0x00000001 /*Ad-Hoc mode*/
+#define AR5K_BCR_BDMAE 0x00000002 /*DMA enable*/
+#define AR5K_BCR_TQ1FV 0x00000004 /*Use Queue1 for CAB traffic*/
+#define AR5K_BCR_TQ1V 0x00000008 /*Use Queue1 for Beacon
traffic*/
+#define AR5K_BCR_BCGET 0x00000010
+
+/*
+ * First RTS duration register -5211 only-
+ */
+#define AR5K_RTSD0 0x0028 /*Register Address*/
+#define AR5K_RTSD0_6 0x000000ff /*6Mb RTS duration mask
(?)*/
+#define AR5K_RTSD0_6_S 0 /*6Mb RTS duration
shift (?)*/
+#define AR5K_RTSD0_9 0x0000ff00 /*9Mb*/
+#define AR5K_RTSD0_9_S 8
+#define AR5K_RTSD0_12 0x00ff0000 /*12Mb*/
+#define AR5K_RTSD0_12_S 16
+#define AR5K_RTSD0_18 0xff000000 /*16Mb*/
+#define AR5K_RTSD0_18_S 24
+
+
+/*
+ * 0x002c is Beacon Status Register on 5210
+ * and second RTS duration register on 5211
+ */
+
+/*
+ * Beacon status register -5210 only-
+ *
+ * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
+ * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
+ * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
+ * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i
+ * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what
+ * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
+ */
+#define AR5K_BSR 0x002c /*Register Address*/
+#define AR5K_BSR_BDLYSW 0x00000001 /*SW Beacon delay (?)*/
+#define AR5K_BSR_BDLYDMA 0x00000002 /*DMA Beacon delay (?)*/
+#define AR5K_BSR_TXQ1F 0x00000004
+#define AR5K_BSR_ATIMDLY 0x00000008 /*ATIM delay (?)*/
+#define AR5K_BSR_SNPADHOC 0x00000100 /*Ad-hoc mode set (?)*/
+#define AR5K_BSR_SNPBDMAE 0x00000200 /*Beacon DMA enabled (?)*/
+#define AR5K_BSR_SNPTQ1FV 0x00000400 /*Queue1 is used for CAB
traffic (?)*/
+#define AR5K_BSR_SNPTQ1V 0x00000800 /*Queue1 is used for Beacon
traffic (?)*/
+#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /*BCR snapshots are
valid (?)*/
+#define AR5K_BSR_SWBA_CNT 0x00ff0000
+
+/*
+ * Second RTS duration register -5211 only-
+ */
+#define AR5K_RTSD1 0x002c /*Register Address*/
+#define AR5K_RTSD1_24 0x000000ff /*24Mb*/
+#define AR5K_RTSD1_24_S 0
+#define AR5K_RTSD1_36 0x0000ff00 /*36Mb*/
+#define AR5K_RTSD1_36_S 8
+#define AR5K_RTSD1_48 0x00ff0000 /*48Mb*/
+#define AR5K_RTSD1_48_S 16
+#define AR5K_RTSD1_54 0xff000000 /*54Mb*/
+#define AR5K_RTSD1_54_S 24
+
+
+/*
+ * Transmit configuration register
+ */
+#define AR5K_TXCFG 0x0030 /*Register Address*/
+#define AR5K_TXCFG_SDMAMR 0x00000007 /*DMA size*/
+#define AR5K_TXCFG_SDMAMR_S 0
+#define AR5K_TXCFG_B_MODE 0x00000008 /*Set b mode for 5111 (enable
2111)*/
+#define AR5K_TXCFG_TXFSTP 0x00000008 /*TX DMA Stop -5210 only-*/
+#define AR5K_TXCFG_TXFULL 0x000003f0 /*TX Triger level mask*/
+#define AR5K_TXCFG_TXFULL_S 4
+#define AR5K_TXCFG_TXFULL_0B 0x00000000
+#define AR5K_TXCFG_TXFULL_64B 0x00000010
+#define AR5K_TXCFG_TXFULL_128B 0x00000020
+#define AR5K_TXCFG_TXFULL_192B 0x00000030
+#define AR5K_TXCFG_TXFULL_256B 0x00000040
+#define AR5K_TXCFG_TXCONT_EN 0x00000080
+#define AR5K_TXCFG_DMASIZE 0x00000100 /*flag for passing DMA size
-non 5210*/
+#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /*enable jumbo frames
transmition (?) -non 5210*/
+#define AR5K_TXCFG_RTSRND 0x00001000 /*non 5210*/
+#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /*non 5210*/
+#define AR5K_TXCFG_RDY_DIS 0x00004000 /*non 5210*/
+
+/*
+ * Receive configuration register
+ */
+#define AR5K_RXCFG 0x0034 /*Register Address*/
+#define AR5K_RXCFG_SDMAMW 0x00000007 /*DMA size*/
+#define AR5K_RXCFG_SDMAMW_S 0
+#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /*default antenna*/
+#define AR5K_RXCFG_ZLFDMA 0x00000010 /*zero-length DMA*/
+#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /*enable jumbo frames recieve
(?) -non 5210*/
+#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /*wrap jumbo frames (?) -non
5210*/
+
+/*
+ * Receive jumbo descriptor last address register
+ * Only found in 5211 (?)
+ */
+#define AR5K_RXJLA 0x0038
+
+/*
+ * MIB control register
+ */
+#define AR5K_MIBC 0x0040 /*Register Address*/
+#define AR5K_MIBC_COW 0x00000001
+#define AR5K_MIBC_FMC 0x00000002 /*Freeze Mib Counters (?)*/
+#define AR5K_MIBC_CMC 0x00000004 /*Clean Mib Counters (?)*/
+#define AR5K_MIBC_MCS 0x00000008
+
+/*
+ * Timeout prescale register
+ */
+#define AR5K_TOPS 0x0044
+#define AR5K_TOPS_M 0x0000ffff /*non 5210*/
+
+/*
+ * Receive timeout register (no frame received)
+ */
+#define AR5K_RXNOFRM 0x0048
+#define AR5K_RXNOFRM_M 0x000003ff /*non 5210*/
+
+/*
+ * Transmit timeout register (no frame sent)
+ */
+#define AR5K_TXNOFRM 0x004c
+#define AR5K_TXNOFRM_M 0x000003ff /*non 5210*/
+#define AR5K_TXNOFRM_QCU 0x000ffc00 /*non 5210*/
+
+/*
+ * Receive frame gap timeout register
+ */
+#define AR5K_RPGTO 0x0050
+#define AR5K_RPGTO_M 0x000003ff /*non 5210*/
+
+/*
+ * Receive frame count limit register
+ */
+#define AR5K_RFCNT 0x0054
+#define AR5K_RFCNT_M 0x0000001f /*non 5210*/
+#define AR5K_RFCNT_RFCL 0x0000000f /*5210*/
+
+/*
+ * Misc settings register
+ */
+#define AR5K_MISC 0x0058 /*Register Address*/
+#define AR5K_MISC_DMA_OBS_M 0x000001e0
+#define AR5K_MISC_DMA_OBS_S 5
+#define AR5K_MISC_MISC_OBS_M 0x00000e00
+#define AR5K_MISC_MISC_OBS_S 9
+#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
+#define AR5K_MISC_MAC_OBS_LSB_S 12
+#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
+#define AR5K_MISC_MAC_OBS_MSB_S 15
+#define AR5K_MISC_LED_DECAY 0x001c0000 /*5210*/
+#define AR5K_MISC_LED_BLINK 0x00e00000 /*5210*/
+
+/*
+ * QCU/DCU clock gating register (5311)
+ */
+#define AR5K_QCUDCU_CLKGT 0x005c /*Register
Address (?)*/
+#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /*Mask for QCU clock*/
+#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /*Mask for DCU clock*/
+
+/*
+ * Interrupt Status Registers
+ *
+ * For 5210 there is only one status register but for
+ * 5211/5212 we have one primary and 4 secondary registers.
+ * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
+ * Most of these bits are common for all chipsets.
+ */
+#define AR5K_ISR 0x001c /*Register Address
(5210)*/
+#define AR5K_PISR 0x0080 /*Register Address
(5211/5212)*/
+#define AR5K_ISR_RXOK 0x00000001 /*Frame successfuly recieved*/
+#define AR5K_ISR_RXDESC 0x00000002 /*RX descriptor
request*/
+#define AR5K_ISR_RXERR 0x00000004 /*Receive error*/
+#define AR5K_ISR_RXNOFRM 0x00000008 /*No frame received (receive
timeout)*/
+#define AR5K_ISR_RXEOL 0x00000010 /*Empty RX descriptor*/
+#define AR5K_ISR_RXORN 0x00000020 /*Receive FIFO overrun*/
+#define AR5K_ISR_TXOK 0x00000040 /*Frame successfuly transmited*/
+#define AR5K_ISR_TXDESC 0x00000080 /*TX descriptor
request*/
+#define AR5K_ISR_TXERR 0x00000100 /*Transmit error*/
+#define AR5K_ISR_TXNOFRM 0x00000200 /*No frame transmited (transmit
timeout)*/
+#define AR5K_ISR_TXEOL 0x00000400 /*Empty TX descriptor*/
+#define AR5K_ISR_TXURN 0x00000800 /*Transmit FIFO underrun*/
+#define AR5K_ISR_MIB 0x00001000 /*Update MIB counters*/
+#define AR5K_ISR_SWI 0x00002000
+#define AR5K_ISR_RXPHY 0x00004000 /*PHY error*/
+#define AR5K_ISR_RXKCM 0x00008000
+#define AR5K_ISR_SWBA 0x00010000 /*Software beacon alert*/
+#define AR5K_ISR_BRSSI 0x00020000
+#define AR5K_ISR_BMISS 0x00040000 /*Beacon missed*/
+#define AR5K_ISR_HIUERR 0x00080000 /*Host Interface Unit
error -non 5210*/
+#define AR5K_ISR_BNR 0x00100000 /*Beacon not ready -non 5210*/
+#define AR5K_ISR_MCABT 0x00100000 /*5210*/
+#define AR5K_ISR_RXCHIRP 0x00200000 /*5212 only*/
+#define AR5K_ISR_SSERR 0x00200000 /*5210 only*/
+#define AR5K_ISR_DPERR 0x00400000 /*5210 only*/
+#define AR5K_ISR_TIM 0x00800000 /*non 5210*/
+#define AR5K_ISR_BCNMISC 0x00800000 /*5212 only*/
+#define AR5K_ISR_GPIO 0x01000000 /*GPIO (rf kill)*/
+#define AR5K_ISR_QCBRORN 0x02000000 /*CBR overrun (?) -non 5210*/
+#define AR5K_ISR_QCBRURN 0x04000000 /*CBR underrun (?) -non 5210*/
+#define AR5K_ISR_QTRIG 0x08000000 /*non 5210*/
+
+/*
+ * Secondary status registers (5211/5212) (0 - 4)
+ *
+ * I guess from the names that these give the status for each
+ * queue, that's why only masks are defined here, haven't got
+ * any info about them (couldn't find them anywhere in ar5k code).
+ */
+#define AR5K_SISR0 0x0084 /*Register Address
(5211/5212)*/
+#define AR5K_SISR0_QCU_TXOK 0x000003ff /*Mask for QCU_TXOK*/
+#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /*Mask for QCU_TXDESC*/
+
+#define AR5K_SISR1 0x0088 /*Register Address
(5211/5212)*/
+#define AR5K_SISR1_QCU_TXERR 0x000003ff /*Mask for QCU_TXERR*/
+#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /*Mask for QCU_TXEOL*/
+
+#define AR5K_SISR2 0x008c /*Register Address
(5211/5212)*/
+#define AR5K_SISR2_QCU_TXURN 0x000003ff /*Mask for QCU_TXURN*/
+#define AR5K_SISR2_MCABT 0x00100000
+#define AR5K_SISR2_SSERR 0x00200000
+#define AR5K_SISR2_DPERR 0x00400000
+#define AR5K_SISR2_TIM 0x01000000 /*5212 only*/
+#define AR5K_SISR2_CAB_END 0x02000000 /*5212 only*/
+#define AR5K_SISR2_DTIM_SYNC 0x04000000 /*5212 only*/
+#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /*5212 only*/
+#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /*5212 only*/
+#define AR5K_SISR2_DTIM 0x20000000 /*5212 only*/
+
+#define AR5K_SISR3 0x0090 /*Register Address
(5211/5212)*/
+#define AR5K_SISR3_QCBRORN 0x000003ff /*Mask for QCBRORN*/
+#define AR5K_SISR3_QCBRURN 0x03ff0000 /*Mask for QCBRURN*/
+
+#define AR5K_SISR4 0x0094 /*Register Address
(5211/5212)*/
+#define AR5K_SISR4_QTRIG 0x000003ff /*Mask for QTRIG*/
+
+/*
+ * Shadow read-and-clear interrupt status registers (5211/5212)
+ */
+#define AR5K_RAC_PISR 0x00c0 /*Read and clear PISR*/
+#define AR5K_RAC_SISR0 0x00c4 /*Read and clear SISR0*/
+#define AR5K_RAC_SISR1 0x00c8 /*Read and clear SISR1*/
+#define AR5K_RAC_SISR2 0x00cc /*Read and clear SISR2*/
+#define AR5K_RAC_SISR3 0x00d0 /*Read and clear SISR3*/
+#define AR5K_RAC_SISR4 0x00d4 /*Read and clear SISR4*/
+
+/*
+ * Interrupt Mask Registers
+ *
+ * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
+ * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags
match.
+ */
+#define AR5K_IMR 0x0020 /*Register
Address (5210)*/
+#define AR5K_PIMR 0x00a0 /*Register Address
(5211/5212)*/
+#define AR5K_IMR_RXOK 0x00000001 /*Frame successfuly recieved*/
+#define AR5K_IMR_RXDESC 0x00000002 /*RX descriptor
request*/
+#define AR5K_IMR_RXERR 0x00000004 /*Receive error*/
+#define AR5K_IMR_RXNOFRM 0x00000008 /*No frame received (receive
timeout)*/
+#define AR5K_IMR_RXEOL 0x00000010 /*Empty RX descriptor*/
+#define AR5K_IMR_RXORN 0x00000020 /*Receive FIFO overrun*/
+#define AR5K_IMR_TXOK 0x00000040 /*Frame successfuly transmited*/
+#define AR5K_IMR_TXDESC 0x00000080 /*TX descriptor
request*/
+#define AR5K_IMR_TXERR 0x00000100 /*Transmit error*/
+#define AR5K_IMR_TXNOFRM 0x00000200 /*No frame transmited (transmit
timeout)*/
+#define AR5K_IMR_TXEOL 0x00000400 /*Empty TX descriptor*/
+#define AR5K_IMR_TXURN 0x00000800 /*Transmit FIFO underrun*/
+#define AR5K_IMR_MIB 0x00001000 /*Update MIB counters*/
+#define AR5K_IMR_SWI 0x00002000
+#define AR5K_IMR_RXPHY 0x00004000 /*PHY error*/
+#define AR5K_IMR_RXKCM 0x00008000
+#define AR5K_IMR_SWBA 0x00010000 /*Software beacon alert*/
+#define AR5K_IMR_BRSSI 0x00020000
+#define AR5K_IMR_BMISS 0x00040000 /*Beacon missed*/
+#define AR5K_IMR_HIUERR 0x00080000 /*Host Interface Unit
error -non 5210*/
+#define AR5K_IMR_BNR 0x00100000 /*Beacon not ready -non 5210*/
+#define AR5K_IMR_MCABT 0x00100000 /*5210*/
+#define AR5K_IMR_RXCHIRP 0x00200000 /*5212 only*/
+#define AR5K_IMR_SSERR 0x00200000 /*5210 only*/
+#define AR5K_IMR_DPERR 0x00400000 /*5210 only*/
+#define AR5K_IMR_TIM 0x00800000 /*non 5210*/
+#define AR5K_IMR_BCNMISC 0x00800000 /*5212 only*/
+#define AR5K_IMR_GPIO 0x01000000 /*GPIO (rf kill)*/
+#define AR5K_IMR_QCBRORN 0x02000000 /*CBR overrun (?) -non 5210*/
+#define AR5K_IMR_QCBRURN 0x04000000 /*CBR underrun (?) -non 5210*/
+#define AR5K_IMR_QTRIG 0x08000000 /*non 5210*/
+
+/*
+ * Secondary interrupt mask registers (5211/5212) (0 - 4)
+ */
+#define AR5K_SIMR0 0x00a4 /*Register Address
(5211/5212)*/
+#define AR5K_SIMR0_QCU_TXOK 0x000003ff /*Mask for QCU_TXOK*/
+#define AR5K_SIMR0_QCU_TXOK_S 0
+#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /*Mask for QCU_TXDESC*/
+#define AR5K_SIMR0_QCU_TXDESC_S 16
+
+#define AR5K_SIMR1 0x00a8 /*Register Address
(5211/5212)*/
+#define AR5K_SIMR1_QCU_TXERR 0x000003ff /*Mask for QCU_TXERR*/
+#define AR5K_SIMR1_QCU_TXERR_S 0
+#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /*Mask for QCU_TXEOL*/
+#define AR5K_SIMR1_QCU_TXEOL_S 16
+
+#define AR5K_SIMR2 0x00ac /*Register Address
(5211/5212)*/
+#define AR5K_SIMR2_QCU_TXURN 0x000003ff /*Mask for QCU_TXURN*/
+#define AR5K_SIMR2_QCU_TXURN_S 0
+#define AR5K_SIMR2_MCABT 0x00100000
+#define AR5K_SIMR2_SSERR 0x00200000
+#define AR5K_SIMR2_DPERR 0x00400000
+#define AR5K_SIMR2_TIM 0x01000000 /*5212 only*/
+#define AR5K_SIMR2_CAB_END 0x02000000 /*5212 only*/
+#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /*5212 only*/
+#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /*5212 only*/
+#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /*5212 only*/
+#define AR5K_SIMR2_DTIM 0x20000000 /*5212 only*/
+
+#define AR5K_SIMR3 0x00b0 /*Register Address
(5211/5212)*/
+#define AR5K_SIMR3_QCBRORN 0x000003ff /*Mask for QCBRORN*/
+#define AR5K_SIMR3_QCBRORN_S 0
+#define AR5K_SIMR3_QCBRURN 0x03ff0000 /*Mask for QCBRURN*/
+#define AR5K_SIMR3_QCBRURN_S 16
+
+#define AR5K_SIMR4 0x00b4 /*Register Address
(5211/5212)*/
+#define AR5K_SIMR4_QTRIG 0x000003ff /*Mask for QTRIG*/
+#define AR5K_SIMR4_QTRIG_S 0
+
+
+/*
+ * Decompression mask registers (5212)
+ */
+#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address
(?)*/
+#define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/
+
+/*
+ * Decompression configuration registers (5212)
+ */
+#define AR5K_DCCFG 0x0420
+
+/*
+ * Compression configuration registers (5212)
+ */
+#define AR5K_CCFG 0x0600
+#define AR5K_CCFG_CUP 0x0604
+
+/*
+ * Compression performance counter registers (5212)
+ */
+#define AR5K_CPC0 0x0610 /*Compression performance
counter 0*/
+#define AR5K_CPC1 0x0614 /*Compression performance
counter 1*/
+#define AR5K_CPC2 0x0618 /*Compression performance
counter 2*/
+#define AR5K_CPC3 0x061c /*Compression performance
counter 3*/
+#define AR5K_CPCORN 0x0620 /*Compression performance
overrun (?)*/
+
+
+/*
+ * Queue control unit (QCU) registers (5211/5212)
+ *
+ * Card has 12 TX Queues but i see that only 0-9 are used (?)
+ * both in binary HAL (see ah.h) and ar5k. Each queue has it's own
+ * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
+ * configuration register (0x08c0 - 0x08ec), a ready time configuration
+ * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
+ * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
+ * global registers, QCU transmit enable/disable and "one shot arm (?)"
+ * set/clear, which contain status for all queues (we shift by 1 for each
+ * queue). To access these registers easily we define some macros here
+ * that are used inside HAL. For more infos check out *_tx_queue functs.
+ *
+ * TODO: Boundary checking on macros (here?)
+ */
+
+/*
+ * Generic QCU Register access macros
+ */
+#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
+#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
+#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
+
+/*
+ * QCU Transmit descriptor pointer registers
+ */
+#define AR5K_QCU_TXDP_BASE 0x0800 /*Register Address - Queue0
TXDP*/
+#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
+
+/*
+ * QCU Transmit enable register
+ */
+#define AR5K_QCU_TXE 0x0840
+#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
+#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
+
+/*
+ * QCU Transmit disable register
+ */
+#define AR5K_QCU_TXD 0x0880
+#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
+#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
+
+/*
+ * QCU Constant Bit Rate configuration registers
+ */
+#define AR5K_QCU_CBRCFG_BASE 0x08c0 /*Register Address -
Queue0 CBRCFG*/
+#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /*CBR Interval
mask*/
+#define AR5K_QCU_CBRCFG_INTVAL_S 0
+#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /*CBR overrun
threshold mask*/
+#define AR5K_QCU_CBRCFG_ORN_THRES_S 24
+#define AR5K_QUEUE_CBRCFG(_q)
AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
+
+/*
+ * QCU Ready time configuration registers
+ */
+#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /*Register Address -
Queue0 RDYTIMECFG*/
+#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /*Ready time
interval mask*/
+#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
+#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /*Ready time
duration mask*/
+#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /*Ready time
enable mask*/
+#define AR5K_QUEUE_RDYTIMECFG(_q)
AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
+
+/*
+ * QCU one shot arm set registers
+ */
+#define AR5K_QCU_ONESHOTARM_SET 0x0940 /*Register Address -QCU
"one shot arm set (?)"*/
+#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
+
+/*
+ * QCU one shot arm clear registers
+ */
+#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /*Register Address -QCU
"one shot arm clear (?)"*/
+#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
+
+/*
+ * QCU misc registers
+ */
+#define AR5K_QCU_MISC_BASE 0x09c0 /*Register
Address -Queue0 MISC*/
+#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /*Frame
sheduling mask*/
+#define AR5K_QCU_MISC_FRSHED_ASAP 0 /*ASAP*/
+#define AR5K_QCU_MISC_FRSHED_CBR 1 /*Constant Bit
Rate*/
+#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /*DMA Beacon
alert (GaTed ?)*/
+#define AR5K_QCU_MISC_FRSHED_TIM_GT 3
+#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /*Beacon sent
gated (?)*/
+#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /*Oneshot
enable*/
+#define AR5K_QCU_MISC_CBREXP 0x00000020 /*CBR expired
(normal queue)*/
+#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /*CBR expired
(beacon queue)*/
+#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /*Beacons
enabled*/
+#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /*CBR threshold
enabled (?)*/
+#define AR5K_QCU_MISC_TXE 0x00000200 /*TXE reset
when RDYTIME enalbed (?)*/
+#define AR5K_QCU_MISC_CBR 0x00000400 /*CBR threshold
reset (?)*/
+#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /*DCU reset
(?)*/
+#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
+
+
+/*
+ * QCU status registers
+ */
+#define AR5K_QCU_STS_BASE 0x0a00 /*Register Address -
Queue0 STS*/
+#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /*Frames pending
counter*/
+#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /*CBR expired counter
(?)*/
+#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
+
+/*
+ * QCU ready time shutdown register
+ */
+#define AR5K_QCU_RDYTIMESHDN 0x0a40
+#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
+
+/*
+ * QCU compression buffer base registers (5212 only)
+ */
+#define AR5K_QCU_CBB_SELECT 0x0b00
+#define AR5K_QCU_CBB_ADDR 0x0b04
+
+/*
+ * QCU compression buffer configuration register (5212 only)
+ */
+#define AR5K_QCU_CBCFG 0x0b08
+
+
+
+/*
+ * Distributed Coordination Function (DCF) control unit (DCU)
+ * registers (5211/5212)
+ *
+ * These registers control the various characteristics of each queue
+ * for 802.11e (WME) combatibility so they go together with
+ * QCU registers in pairs. For each queue we have a QCU mask register,
+ * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
+ * a retry limit register (0x1080 - 0x10ac), a channel time register
+ * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
+ * a sequence number register (0x1140 - 0x116c). It seems that "global"
+ * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
+ * We use the same macros here for easier register access.
+ *
+ */
+
+/*
+ * DCU QCU mask registers
+ */
+#define AR5K_DCU_QCUMASK_BASE 0x1000 /*Register Address -Queue0
DCU_QCUMASK*/
+#define AR5K_DCU_QCUMASK_M 0x000003ff
+#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
+
+/*
+ * DCU local Inter Frame Space settings register
+ */
+#define AR5K_DCU_LCL_IFS_BASE 0x1040 /*Register
Address -Queue0 DCU_LCL_IFS*/
+#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /*Minimum
Contention Window*/
+#define AR5K_DCU_LCL_IFS_CW_MIN_S 0
+#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /*Maximum
Contention Window*/
+#define AR5K_DCU_LCL_IFS_CW_MAX_S 10
+#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /*Arbitrated
Interframe Space*/
+#define AR5K_DCU_LCL_IFS_AIFS_S 20
+#define AR5K_QUEUE_DFS_LOCAL_IFS(_q)
AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
+
+/*
+ * DCU retry limit registers
+ */
+#define AR5K_DCU_RETRY_LMT_BASE 0x1080
/*Register Address -Queue0 DCU_RETRY_LMT*/
+#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /*Short retry limit
mask*/
+#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0
+#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /*Long retry limit
mask*/
+#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4
+#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /*Station short retry
limit mask (?)*/
+#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8
+#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /*Station long retry
limit mask (?)*/
+#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14
+#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)
AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
+
+/*
+ * DCU channel time registers
+ */
+#define AR5K_DCU_CHAN_TIME_BASE 0x10c0
/*Register Address -Queue0 DCU_CHAN_TIME*/
+#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /*Channel time
duration*/
+#define AR5K_DCU_CHAN_TIME_DUR_S 0
+#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /*Enable
channel time*/
+#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q)
AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
+
+/*
+ * DCU misc registers
+ *
+ * For some of the registers i couldn't find in the code
+ * (only backoff stuff is there realy) i tried to match the
+ * names with 802.11e parameters etc, so i guess VIRTCOL here
+ * means Virtual Collision and HCFPOLL means Hybrid Coordination
+ * factor Poll (CF- Poll). ARBLOCK_CTL_GLOBAL is used for beacon
+ * queue and CAB queue but i couldn't find any more infos.
+ */
+#define AR5K_DCU_MISC_BASE 0x1100 /*Register
Address -Queue0 DCU_MISC*/
+#define AR5K_DCU_MISC_BACKOFF 0x000007ff /*Mask for
backoff setting (?)*/
+#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /*Enable backoff while
bursting*/
+#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /*CF - Poll
(?)*/
+#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /*Persistent
backoff (?)*/
+#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /*Enable frame
pre-fetch (?)*/
+#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /*Mask for
Virtual Collision (?)*/
+#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
+#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1
+#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2
+#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /*Beacon enable
(?)*/
+#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000
+#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
+#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0
+#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1
+#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
+#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000
+#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /*Disable
sequence number increment (?)*/
+#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /*Disable
post-frame backoff (?)*/
+#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /*Virtual
Collision policy (?)*/
+#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
+#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /*Sequence
number control (?)*/
+#define AR5K_QUEUE_DFS_MISC(_q)
AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
+
+/*
+ * DCU frame sequence number registers
+ */
+#define AR5K_DCU_SEQNUM_BASE 0x1140
+#define AR5K_DCU_SEQNUM_M 0x00000fff
+#define AR5K_QUEUE_DFS_SEQNUM(_q)
AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
+
+/*
+ * DCU global IFS SIFS registers
+ */
+#define AR5K_DCU_GBL_IFS_SIFS 0x1030
+#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
+
+/*
+ * DCU global IFS slot interval registers
+ */
+#define AR5K_DCU_GBL_IFS_SLOT 0x1070
+#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
+
+/*
+ * DCU global IFS EIFS registers
+ */
+#define AR5K_DCU_GBL_IFS_EIFS 0x10b0
+#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
+
+/*
+ * DCU global IFS misc registers
+ */
+#define AR5K_DCU_GBL_IFS_MISC 0x10f0
/*Register Address*/
+#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
+#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /*Turbo
mode (?)*/
+#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /*SIFS
Duration mask (?)*/
+#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
+#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
+
+/*
+ * DCU frame prefetch control register
+ */
+#define AR5K_DCU_FP 0x1230
+
+/*
+ * DCU transmit pause control/status register
+ */
+#define AR5K_DCU_TXP 0x1270 /*Register Address*/
+#define AR5K_DCU_TXP_M 0x000003ff /*Tx pause mask (?)*/
+#define AR5K_DCU_TXP_STATUS 0x00010000 /*Tx pause status (?)*/
+
+/*
+ * DCU transmit filter register
+ */
+#define AR5K_DCU_TX_FILTER 0x1038
+
+/*
+ * DCU clear transmit filter register
+ */
+#define AR5K_DCU_TX_FILTER_CLR 0x143c
+
+/*
+ * DCU set transmit filter register
+ */
+#define AR5K_DCU_TX_FILTER_SET 0x147c
+
+/*
+ * Reset control register
+ *
+ * 4 and 8 are not used in 5211/5212 and
+ * 2 means "baseband reset" on 5211/5212.
+ */
+#define AR5K_RESET_CTL 0x4000 /*Register Address*/
+#define AR5K_RESET_CTL_PCU 0x00000001 /*Protocol Control Unit reset*/
+#define AR5K_RESET_CTL_DMA 0x00000002 /*DMA (Rx/Tx) reset -5210 only*/
+#define AR5K_RESET_CTL_BASEBAND 0x00000002 /*Baseband reset
(5211/5212)*/
+#define AR5K_RESET_CTL_MAC 0x00000004 /*MAC reset (PCU+Baseband ?)
-5210 only*/
+#define AR5K_RESET_CTL_PHY 0x00000008 /*PHY reset -5210 only*/
+#define AR5K_RESET_CTL_PCI 0x00000010 /*PCI Core reset (interrupts
etc)*/
+#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA |
\
+ AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY)
+
+/*
+ * Sleep control register
+ */
+#define AR5K_SLEEP_CTL 0x4004 /*Register
Address*/
+#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /*Sleep duration mask*/
+#define AR5K_SLEEP_CTL_SLDUR_S 0
+#define AR5K_SLEEP_CTL_SLE 0x00030000 /*Sleep enable mask*/
+#define AR5K_SLEEP_CTL_SLE_S 16
+#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /*Force chip
awake*/
+#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /*Force chip sleep*/
+#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
+#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /*non 5210*/
+
+/*
+ * Interrupt pending register
+ */
+#define AR5K_INTPEND 0x4008
+#define AR5K_INTPEND_M 0x00000001
+
+/*
+ * Sleep force register
+ */
+#define AR5K_SFR 0x400c
+#define AR5K_SFR_M 0x00000001
+
+/*
+ * PCI configuration register
+ *
+ * (5210) = prop is also pressent at 5210 else it's only
+ * for 5211/5212. Also some props are only present at 5210.
+ */
+#define AR5K_PCICFG 0x4010 /*Register
Address*/
+#define AR5K_PCICFG_EEAE 0x00000001 /*Eeprom access enable
-5210 only*/
+#define AR5K_PCICFG_CLKRUNEN 0x00000004 /*CLKRUN enable*/
+#define AR5K_PCICFG_EESIZE 0x00000018 /*Mask for EEPROM size*/
+#define AR5K_PCICFG_EESIZE_S 3
+#define AR5K_PCICFG_EESIZE_4K 0 /*4K*/
+#define AR5K_PCICFG_EESIZE_8K 1 /*8K*/
+#define AR5K_PCICFG_EESIZE_16K 2 /*16K*/
+#define AR5K_PCICFG_EESIZE_FAIL 3 /*Failed to get
size (?)*/
+#define AR5K_PCICFG_LED 0x00000060 /*Led status*/
+#define AR5K_PCICFG_LED_NONE 0x00000000 /*Default*/
+#define AR5K_PCICFG_LED_PEND 0x00000020 /*Scan / Auth pending
(5210)*/
+#define AR5K_PCICFG_LED_ASSOC 0x00000040 /*Associated (5210)*/
+#define AR5K_PCICFG_BUS_SEL 0x00000380 /*Mask for "bus
select" (?)*/
+#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /*Disable CBE
fix (?)*/
+#define AR5K_PCICFG_SL_INTEN 0x00000800 /*Enable interrupts
when asleep (?) (5210)*/
+#define AR5K_PCICFG_LED_BCTL 0x00001000 /*Led blink (?) -5210
only*/
+#define AR5K_PCICFG_SL_INPEN 0x00002800 /*Sleep even whith
pending interrupts (?) (5210)*/
+#define AR5K_PCICFG_SPWR_DN 0x00010000 /*Mask for power status
(5210)*/
+#define AR5K_PCICFG_LEDMODE 0x000e0000 /*Ledmode*/
+#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /*Blink on standard
traffic*/
+#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /*Default mode (blink
on any traffic)*/
+#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /*Some other
blinking mode (?)*/
+#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /*Random blinking (?)*/
+#define AR5K_PCICFG_LEDBLINK 0x00700000
+#define AR5K_PCICFG_LEDBLINK_S 20
+#define AR5K_PCICFG_LEDSLOW 0x00800000 /*Slow led blink rate
(?)*/
+#define AR5K_PCICFG_LEDSTATE \
+ (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
+ AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
+
+/*
+ * "General Purpose Input/Output" (GPIO) control register
+ *
+ * I'm not sure about this but after looking at the code
+ * for all chipsets here is what i got.
+ *
+ * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)
+ * Mode 0 -> always input
+ * Mode 1 -> output when GPIODO for this GPIO is set to 0
+ * Mode 2 -> output when GPIODO for this GPIO is set to 1
+ * Mode 3 -> always output
+ *
+ * For more infos check out get_gpio/set_gpio and
+ * set_gpio_input/set_gpio_output functs.
+ * For more infos on gpio interrupt check out set_gpio_intr.
+ */
+#define AR5K_NUM_GPIO 6
+
+#define AR5K_GPIOCR 0x4014 /*Register
Address*/
+#define AR5K_GPIOCR_INT_ENA 0x00008000 /*Enable GPIO
interrupt*/
+#define AR5K_GPIOCR_INT_SELL 0x00000000 /*Generate interrupt
when pin is off (?)*/
+#define AR5K_GPIOCR_INT_SELH 0x00010000 /*Generate interrupt
when pin is on*/
+#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /*Mode 0 for pin n*/
+#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /*Mode 1 for pin n*/
+#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /*Mode 2 for pin n*/
+#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /*Mode 3 for pin n*/
+#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /*Interrupt for GPIO
pin n*/
+
+/*
+ * "General Purpose Input/Output" (GPIO) data output register
+ */
+#define AR5K_GPIODO 0x4018
+
+/*
+ * "General Purpose Input/Output" (GPIO) data input register
+ */
+#define AR5K_GPIODI 0x401c
+#define AR5K_GPIODI_M 0x0000002f
+
+
+/*
+ * Silicon revision register
+ */
+#define AR5K_SREV 0x4020 /*Register Address*/
+#define AR5K_SREV_REV 0x0000000f /*Mask for revision*/
+#define AR5K_SREV_REV_S 0
+#define AR5K_SREV_VER 0x000000ff /*Mask for version*/
+#define AR5K_SREV_VER_S 4
+
+
+
+/*====EEPROM REGISTERS====*/
+
+/*
+ * EEPROM access registers
+ *
+ * Here we got a difference between 5210/5211-12
+ * read data register for 5210 is at 0x6800 and
+ * status register is at 0x6c00. There is also
+ * no eeprom command register on 5210 and the
+ * offsets are different.
+ *
+ * To read eeprom data for a specific offset:
+ * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
+ * read AR5K_EEPROM_BASE +(4 * offset)
+ * check the eeprom status register
+ * and read eeprom data register.
+ *
+ * 5211 - write offset to AR5K_EEPROM_BASE
+ * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD
+ * check the eeprom status register
+ * and read eeprom data register.
+ *
+ * To write eeprom data for a specific offset:
+ * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
+ * write data to AR5K_EEPROM_BASE +(4 * offset)
+ * check the eeprom status register
+ * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
+ * 5212 write offset to AR5K_EEPROM_BASE
+ * write data to data register
+ * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD
+ * check the eeprom status register
+ *
+ * For more infos check eeprom_* functs and the ar5k.c
+ * file posted in madwifi-devel mailing list.
+ * http://sourceforge.net/mailarchive/message.php?msg_id=8966525
+ *
+ */
+#define AR5K_EEPROM_BASE 0x6000
+
+/*
+ * Common ar5xxx EEPROM data offset (set these on AR5K_EEPROM_BASE)
+ */
+#define AR5K_EEPROM_MAGIC 0x003d
+#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5
+#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
+#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
+#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
+
+#define AR5K_EEPROM_PROTECT 0x003f
+#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001
+#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002
+#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004
+#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
+#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010
+#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
+#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040
+#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
+#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100
+#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
+#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400
+#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
+#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000
+#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
+#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000
+#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
+#define AR5K_EEPROM_REG_DOMAIN 0x00bf
+#define AR5K_EEPROM_INFO_BASE 0x00c0
+#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
+#define AR5K_EEPROM_INFO_CKSUM 0xffff
+#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
+
+#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
+#define AR5K_EEPROM_VERSION_3_0 0x3000
+#define AR5K_EEPROM_VERSION_3_1 0x3001
+#define AR5K_EEPROM_VERSION_3_2 0x3002
+#define AR5K_EEPROM_VERSION_3_3 0x3003
+#define AR5K_EEPROM_VERSION_3_4 0x3004
+#define AR5K_EEPROM_VERSION_4_0 0x4000
+#define AR5K_EEPROM_VERSION_4_1 0x4001
+#define AR5K_EEPROM_VERSION_4_2 0x4002
+#define AR5K_EEPROM_VERSION_4_3 0x4003
+#define AR5K_EEPROM_VERSION_4_6 0x4006
+#define AR5K_EEPROM_VERSION_4_7 0x3007
+
+#define AR5K_EEPROM_MODE_11A 0
+#define AR5K_EEPROM_MODE_11B 1
+#define AR5K_EEPROM_MODE_11G 2
+
+#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2)
+#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A)
& 0x1)
+#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B)
& 0x1)
+#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G)
& 0x1)
+#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
+#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
+#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
+#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
+#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
+
+#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
+#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
+#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
+#define AR5K_EEPROM_RFKILL_POLARITY_S 1
+
+/* Newer EEPROMs are using a different offset */
+#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
+ (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
+
+#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
+#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
+#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
+
+#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
+#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
+#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
+#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)
+
+/* Since 3.1 */
+#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
+#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
+
+/* Misc values available since EEPROM 4.0 */
+#define AR5K_EEPROM_MISC0 0x00c4
+#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
+#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
+#define AR5K_EEPROM_MISC1 0x00c5
+#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
+#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
+
+/*
+ * EEPROM data register
+ */
+#define AR5K_EEPROM_DATA_5211 0x6004
+#define AR5K_EEPROM_DATA_5210 0x6800
+#define AR5K_EEPROM_DATA (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
+
+/*
+ * EEPROM command register
+ */
+#define AR5K_EEPROM_CMD 0x6008 /*Register
Addres*/
+#define AR5K_EEPROM_CMD_READ 0x00000001 /*EEPROM read*/
+#define AR5K_EEPROM_CMD_WRITE 0x00000002 /*EEPROM write*/
+#define AR5K_EEPROM_CMD_RESET 0x00000004 /*EEPROM reset*/
+
+/*
+ * EEPROM status register
+ */
+#define AR5K_EEPROM_STAT_5210 0x6c00 /*Register Address
-5210*/
+#define AR5K_EEPROM_STAT_5211 0x600c /*Register Address
-5211/5212*/
+#define AR5K_EEPROM_STATUS (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
+#define AR5K_EEPROM_STAT_RDERR 0x00000001 /*EEPROM read failed*/
+#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /*EEPROM read
successful*/
+#define AR5K_EEPROM_STAT_WRERR 0x00000004 /*EEPROM write failed*/
+#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /*EEPROM write
successful*/
+
+/*
+ * EEPROM config register (?)
+ */
+#define AR5K_EEPROM_CFG 0x6010
+
+
+
+/*
+ * Protocol Control Unit (PCU) registers
+ */
+/*Used for checking initial register writes during channel reset (see reset
func)*/
+#define AR5K_PCU_MIN 0x8000
+#define AR5K_PCU_MAX 0x8fff
+
+/*
+ * First station id register (MAC address in lower 32 bits)
+ */
+#define AR5K_STA_ID0 0x8000
+
+/*
+ * Second station id register (MAC address in upper 16 bits)
+ */
+#define AR5K_STA_ID1 0x8004 /*Register
Address*/
+#define AR5K_STA_ID1_AP 0x00010000 /*Set AP mode*/
+#define AR5K_STA_ID1_ADHOC 0x00020000 /*Set Ad-Hoc mode*/
+#define AR5K_STA_ID1_PWR_SV 0x00040000 /*Power save reporting
(?)*/
+#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /*No key
search*/
+#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /*No uapsd polling
-5210 only*/
+#define AR5K_STA_ID1_PCF_5211 0x00100000 /*Enable PCF on
5211/5212*/
+#define AR5K_STA_ID1_PCF_5210 0x00200000 /*Enable PCF on 5210*/
+#define AR5K_STA_ID1_PCF (hal->ah_version == AR5K_AR5210
? \
+ AR5K_STA_ID1_PCF_5210 :
AR5K_STA_ID1_PCF_5211)
+#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /*Use default antenna
on 5211/5212*/
+#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /*Update antenna from
descriptor*/
+#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /*Use default antenna
for RTS (?)*/
+#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /*Use 6Mbit/s
for ACK/CTS (?)*/
+#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /*Use 11b base rate
(for ACK/CTS ?) -non 5210*/
+
+/*
+ * First BSSID register (MAC address, lower 32bits)
+ */
+#define AR5K_BSS_ID0 0x8008
+
+/*
+ * Second BSSID register (MAC address in upper 16 bits)
+ *
+ * AID: Association ID
+ */
+#define AR5K_BSS_ID1 0x800c
+#define AR5K_BSS_ID1_AID 0xffff0000
+#define AR5K_BSS_ID1_AID_S 16
+
+/*
+ * Backoff slot time register
+ */
+#define AR5K_SLOT_TIME 0x8010
+
+/*
+ * ACK/CTS timeout register
+ */
+#define AR5K_TIME_OUT 0x8014 /*Register Address*/
+#define AR5K_TIME_OUT_ACK 0x00001fff /*ACK timeout mask*/
+#define AR5K_TIME_OUT_ACK_S 0
+#define AR5K_TIME_OUT_CTS 0x1fff0000 /*CTS timeout mask*/
+#define AR5K_TIME_OUT_CTS_S 16
+
+/*
+ * RSSI threshold register
+ */
+#define AR5K_RSSI_THR 0x8018 /*Register Address*/
+#define AR5K_RSSI_THR_M 0x000000ff /*Mask for RSSI
threshold -non 5210*/
+#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /*Mask for Beacon
Missed threshold -5210*/
+#define AR5K_RSSI_THR_BMISS_5210_S 8
+#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /*Mask for Beacon
Missed threshold -5211/5212*/
+#define AR5K_RSSI_THR_BMISS_5211_S 8
+#define AR5K_RSSI_THR_BMISS (hal->ah_version == AR5K_AR5210
? \
+ AR5K_RSSI_THR_BMISS_5210 :
AR5K_RSSI_THR_BMISS_5211)
+#define AR5K_RSSI_THR_BMISS_S 8
+
+/*
+ * 5210 has more PCU registers because there is no QCU/DCU
+ * so queue parameters are set here, this way a lot common
+ * registers have different address for 5210. To make things
+ * easier we define a macro based on hal->ah_version for common
+ * registers with different addresses and common flags.
+ */
+
+/*
+ * Retry limit register
+ *
+ * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
+ */
+#define AR5K_NODCU_RETRY_LMT 0x801c /*Register
Address*/
+#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /*Short retry limit
mask*/
+#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
+#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /*Long retry mask*/
+#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
+#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /*Station short retry
limit mask*/
+#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
+#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /*Station long retry
limit mask*/
+#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
+#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /*Minimum contention
window mask*/
+#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
+
+/*
+ * Transmit latency register
+ */
+#define AR5K_USEC_5210 0x8020 /*Register
Address (5210)*/
+#define AR5K_USEC_5211 0x801c /*Register
Address (5211/5212)*/
+#define AR5K_USEC (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_USEC_5210 : AR5K_USEC_5211)
+#define AR5K_USEC_1 0x0000007f
+#define AR5K_USEC_1_S 0
+#define AR5K_USEC_32 0x00003f80
+#define AR5K_USEC_32_S 7
+#define AR5K_USEC_TX_LATENCY_5211 0x007fc000
+#define AR5K_USEC_TX_LATENCY_5211_S 14
+#define AR5K_USEC_RX_LATENCY_5211 0x1f800000
+#define AR5K_USEC_RX_LATENCY_5211_S 23
+#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /*also for 5311*/
+#define AR5K_USEC_TX_LATENCY_5210_S 14
+#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /*also for 5311*/
+#define AR5K_USEC_RX_LATENCY_5210_S 20
+
+/*
+ * PCU beacon control register
+ */
+#define AR5K_BEACON_5210 0x8024
+#define AR5K_BEACON_5211 0x8020
+#define AR5K_BEACON (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_BEACON_5210 : AR5K_BEACON_5211)
+#define AR5K_BEACON_PERIOD 0x0000ffff
+#define AR5K_BEACON_PERIOD_S 0
+#define AR5K_BEACON_TIM 0x007f0000
+#define AR5K_BEACON_TIM_S 16
+#define AR5K_BEACON_ENABLE 0x00800000
+#define AR5K_BEACON_RESET_TSF 0x01000000
+
+/*
+ * CFP period register
+ */
+#define AR5K_CFP_PERIOD_5210 0x8028
+#define AR5K_CFP_PERIOD_5211 0x8024
+#define AR5K_CFP_PERIOD (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
+
+/*
+ * Next beacon time register
+ */
+#define AR5K_TIMER0_5210 0x802c
+#define AR5K_TIMER0_5211 0x8028
+#define AR5K_TIMER0 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
+
+/*
+ * Next DMA beacon alert register
+ */
+#define AR5K_TIMER1_5210 0x8030
+#define AR5K_TIMER1_5211 0x802c
+#define AR5K_TIMER1 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
+
+/*
+ * Next software beacon alert register
+ */
+#define AR5K_TIMER2_5210 0x8034
+#define AR5K_TIMER2_5211 0x8030
+#define AR5K_TIMER2 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
+
+/*
+ * Next ATIM window time register
+ */
+#define AR5K_TIMER3_5210 0x8038
+#define AR5K_TIMER3_5211 0x8034
+#define AR5K_TIMER3 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
+
+
+/*
+ * 5210 First inter frame spacing register (IFS)
+ */
+#define AR5K_IFS0 0x8040
+#define AR5K_IFS0_SIFS 0x000007ff
+#define AR5K_IFS0_SIFS_S 0
+#define AR5K_IFS0_DIFS 0x007ff800
+#define AR5K_IFS0_DIFS_S 11
+
+/*
+ * 5210 Second inter frame spacing register (IFS)
+ */
+#define AR5K_IFS1 0x8044
+#define AR5K_IFS1_PIFS 0x00000fff
+#define AR5K_IFS1_PIFS_S 0
+#define AR5K_IFS1_EIFS 0x03fff000
+#define AR5K_IFS1_EIFS_S 12
+#define AR5K_IFS1_CS_EN 0x04000000
+
+
+/*
+ * CFP duration register
+ */
+#define AR5K_CFP_DUR_5210 0x8048
+#define AR5K_CFP_DUR_5211 0x8038
+#define AR5K_CFP_DUR (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
+
+/*
+ * Receive filter register
+ * TODO: Get these out of ar5xxx.h on ath5k
+ */
+#define AR5K_RX_FILTER_5210 0x804c /*Register Address
(521)*/
+#define AR5K_RX_FILTER_5211 0x803c /*Register Address
(5211/5212)*/
+#define AR5K_RX_FILTER (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
+#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast
frames */
+#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter
multicast frames */
+#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter
broadcast frames */
+#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control
frames */
+#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon
frames */
+#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode
*/
+#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll
frame -5212 only*/
+#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe
requests -5212 only*/
+#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter
phy errors */
+#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter
phy radar errors*/
+#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /*5211 only*/
+#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /*5211 only*/
+#define AR5K_RX_FILTER_PHYERR (hal->ah_version == AR5K_AR5211 ? \
+ AR5K_RX_FILTER_PHYERR_5211 :
AR5K_RX_FILTER_PHYERR_5212)
+#define AR5K_RX_FILTER_RADARERR (hal->ah_version == AR5K_AR5211 ? \
+ AR5K_RX_FILTER_RADARERR_5211 :
AR5K_RX_FILTER_RADARERR_5212)
+/*
+ * Multicast filter register (lower 32 bits)
+ */
+#define AR5K_MCAST_FILTER0_5210 0x8050
+#define AR5K_MCAST_FILTER0_5211 0x8040
+#define AR5K_MCAST_FILTER0 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_MCAST_FILTER0_5210 :
AR5K_MCAST_FILTER0_5211)
+
+/*
+ * Multicast filter register (higher 16 bits)
+ */
+#define AR5K_MCAST_FILTER1_5210 0x8054
+#define AR5K_MCAST_FILTER1_5211 0x8044
+#define AR5K_MCAST_FILTER1 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_MCAST_FILTER1_5210 :
AR5K_MCAST_FILTER1_5211)
+
+
+/*
+ * Transmit mask register (lower 32 bits) (5210)
+ */
+#define AR5K_TX_MASK0 0x8058
+
+/*
+ * Transmit mask register (higher 16 bits) (5210)
+ */
+#define AR5K_TX_MASK1 0x805c
+
+/*
+ * Clear transmit mask (5210)
+ */
+#define AR5K_CLR_TMASK 0x8060
+
+/*
+ * Trigger level register (before transmission) (5210)
+ */
+#define AR5K_TRIG_LVL 0x8064
+
+
+/*
+ * PCU control register
+ *
+ * Only DIS_RX is used in the code, the rest i guess are
+ * for tweaking/diagnostics.
+ */
+#define AR5K_DIAG_SW_5210 0x8068 /*Register
Address (5210)*/
+#define AR5K_DIAG_SW_5211 0x8048 /*Register
Address (5211/5212)*/
+#define AR5K_DIAG_SW (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
+#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001
+#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /*Disable ACKs (?)*/
+#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /*Disable CTSs (?)*/
+#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /*Disable encryption
(?)*/
+#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /*Disable decryption
(?)*/
+#define AR5K_DIAG_SW_DIS_TX 0x00000020 /*Disable transmit
-5210 only*/
+#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /*Disable recieve*/
+#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
+#define AR5K_DIAG_SW_DIS_RX (hal->ah_version == AR5K_AR5210
? \
+ AR5K_DIAG_SW_DIS_RX_5210 :
AR5K_DIAG_SW_DIS_RX_5211)
+#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /*Loopback (i guess it
goes with DIS_TX) -5210 only*/
+#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
+#define AR5K_DIAG_SW_LOOP_BACK (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_DIAG_SW_LOOP_BACK_5210 :
AR5K_DIAG_SW_LOOP_BACK_5211)
+#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100
+#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
+#define AR5K_DIAG_SW_CORR_FCS (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_DIAG_SW_CORR_FCS_5210 :
AR5K_DIAG_SW_CORR_FCS_5211)
+#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200
+#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
+#define AR5K_DIAG_SW_CHAN_INFO (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_DIAG_SW_CHAN_INFO_5210 :
AR5K_DIAG_SW_CHAN_INFO_5211)
+#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /*Scrambler
seed (?)*/
+#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400
+#define AR5K_DIAG_SW_EN_SCRAM_SEED (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_DIAG_SW_EN_SCRAM_SEED_5210 :
AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
+#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /*non 5210*/
+#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /*5210 only*/
+#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /*Scrambler seed mask
(?)*/
+#define AR5K_DIAG_SW_SCRAM_SEED_S 10
+#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /*Disable seqnum
increment (?)-5210 only*/
+#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
+#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000
+#define AR5K_DIAG_SW_FRAME_NV0 (hal->ah_version == AR5K_AR5210
? \
+ AR5K_DIAG_SW_FRAME_NV0_5210 :
AR5K_DIAG_SW_FRAME_NV0_5211)
+#define AR5K_DIAG_SW_OBSPT_M 0x000c0000
+#define AR5K_DIAG_SW_OBSPT_S 18
+
+/*
+ * TSF (clock) register (lower 32 bits)
+ */
+#define AR5K_TSF_L32_5210 0x806c
+#define AR5K_TSF_L32_5211 0x804c
+#define AR5K_TSF_L32 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
+
+/*
+ * TSF (clock) register (higher 32 bits)
+ */
+#define AR5K_TSF_U32_5210 0x8070
+#define AR5K_TSF_U32_5211 0x8050
+#define AR5K_TSF_U32 (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
+
+/*
+ * Last beacon timestamp register
+ */
+#define AR5K_LAST_TSTP 0x8080
+
+/*
+ * ADDAC test register (5211/5212)
+ */
+#define AR5K_ADDAC_TEST 0x8054
+
+/*
+ * Default antenna register (5211/5212)
+ */
+#define AR5K_DEFAULT_ANTENNA 0x8058
+
+
+
+/*
+ * Retry count register (5210)
+ */
+#define AR5K_RETRY_CNT 0x8084 /*Register Address
(5210)*/
+#define AR5K_RETRY_CNT_SSH 0x0000003f /*Station short retry count
(?)*/
+#define AR5K_RETRY_CNT_SLG 0x00000fc0 /*Station long retry count (?)*/
+
+/*
+ * Back-off status register (5210)
+ */
+#define AR5K_BACKOFF 0x8088 /*Register Address
(5210)*/
+#define AR5K_BACKOFF_CW 0x000003ff /*Backoff Contention
Window (?)*/
+#define AR5K_BACKOFF_CNT 0x03ff0000 /*Backoff count (?)*/
+
+
+
+/*
+ * NAV register (current)
+ */
+#define AR5K_NAV_5210 0x808c
+#define AR5K_NAV_5211 0x8084
+#define AR5K_NAV (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_NAV_5210 : AR5K_NAV_5211)
+
+/*
+ * RTS success register
+ */
+#define AR5K_RTS_OK_5210 0x8090
+#define AR5K_RTS_OK_5211 0x8088
+#define AR5K_RTS_OK (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
+
+/*
+ * RTS failure register
+ */
+#define AR5K_RTS_FAIL_5210 0x8094
+#define AR5K_RTS_FAIL_5211 0x808c
+#define AR5K_RTS_FAIL (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
+
+/*
+ * ACK failure register
+ */
+#define AR5K_ACK_FAIL_5210 0x8098
+#define AR5K_ACK_FAIL_5211 0x8090
+#define AR5K_ACK_FAIL (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
+
+/*
+ * FCS failure register
+ */
+#define AR5K_FCS_FAIL_5210 0x809c
+#define AR5K_FCS_FAIL_5211 0x8094
+#define AR5K_FCS_FAIL (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
+
+/*
+ * Beacon count register
+ */
+#define AR5K_BEACON_CNT_5210 0x80a0
+#define AR5K_BEACON_CNT_5211 0x8098
+#define AR5K_BEACON_CNT (hal->ah_version == AR5K_AR5210 ? \
+ AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
+
+
+/*===5212 Specific PCU registers===*/
+
+/*
+ * XR (eXtended Range) mode register
+ */
+#define AR5K_XRMODE 0x80c0
+#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f
+#define AR5K_XRMODE_POLL_TYPE_S 0
+#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c
+#define AR5K_XRMODE_POLL_SUBTYPE_S 2
+#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080
+#define AR5K_XRMODE_SIFS_DELAY 0x000fff00
+#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000
+#define AR5K_XRMODE_FRAME_HOLD_S 20
+
+/*
+ * XR delay register
+ */
+#define AR5K_XRDELAY 0x80c4
+#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff
+#define AR5K_XRDELAY_SLOT_DELAY_S 0
+#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000
+#define AR5K_XRDELAY_CHIRP_DELAY_S 16
+
+/*
+ * XR timeout register
+ */
+#define AR5K_XRTIMEOUT 0x80c8
+#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff
+#define AR5K_XRTIMEOUT_CHIRP_S 0
+#define AR5K_XRTIMEOUT_POLL_M 0xffff0000
+#define AR5K_XRTIMEOUT_POLL_S 16
+
+/*
+ * XR chirp register
+ */
+#define AR5K_XRCHIRP 0x80cc
+#define AR5K_XRCHIRP_SEND 0x00000001
+#define AR5K_XRCHIRP_GAP 0xffff0000
+
+/*
+ * XR stomp register
+ */
+#define AR5K_XRSTOMP 0x80d0
+#define AR5K_XRSTOMP_TX 0x00000001
+#define AR5K_XRSTOMP_RX_ABORT 0x00000002
+#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00
+
+/*
+ * First enhanced sleep register
+ */
+#define AR5K_SLEEP0 0x80d4
+#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff
+#define AR5K_SLEEP0_NEXT_DTIM_S 0
+#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000
+#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000
+#define AR5K_SLEEP0_CABTO 0xff000000
+#define AR5K_SLEEP0_CABTO_S 24
+
+/*
+ * Second enhanced sleep register
+ */
+#define AR5K_SLEEP1 0x80d8
+#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff
+#define AR5K_SLEEP1_NEXT_TIM_S 0
+#define AR5K_SLEEP1_BEACON_TO 0xff000000
+#define AR5K_SLEEP1_BEACON_TO_S 24
+
+/*
+ * Third enhanced sleep register
+ */
+#define AR5K_SLEEP2 0x80dc
+#define AR5K_SLEEP2_TIM_PER 0x0000ffff
+#define AR5K_SLEEP2_TIM_PER_S 0
+#define AR5K_SLEEP2_DTIM_PER 0xffff0000
+#define AR5K_SLEEP2_DTIM_PER_S 16
+
+/*
+ * BSSID mask registers
+ */
+#define AR5K_BSS_IDM0 0x80e0
+#define AR5K_BSS_IDM1 0x80e4
+
+/*
+ * TX power control (TPC) register
+ */
+#define AR5K_TXPC 0x80e8
+#define AR5K_TXPC_ACK_M 0x0000003f
+#define AR5K_TXPC_ACK_S 0
+#define AR5K_TXPC_CTS_M 0x00003f00
+#define AR5K_TXPC_CTS_S 8
+#define AR5K_TXPC_CHIRP_M 0x003f0000
+#define AR5K_TXPC_CHIRP_S 22
+
+/*
+ * Profile count registers
+ */
+#define AR5K_PROFCNT_TX 0x80ec
+#define AR5K_PROFCNT_RX 0x80f0
+#define AR5K_PROFCNT_RXCLR 0x80f4
+#define AR5K_PROFCNT_CYCLE 0x80f8
+
+/*
+ * TSF parameter register
+ */
+#define AR5K_TSF_PARM 0x8104
+#define AR5K_TSF_PARM_INC_M 0x000000ff
+#define AR5K_TSF_PARM_INC_S 0
+
+/*
+ * PHY error filter register
+ */
+#define AR5K_PHY_ERR_FIL 0x810c
+#define AR5K_PHY_ERR_FIL_RADAR 0x00000020
+#define AR5K_PHY_ERR_FIL_OFDM 0x00020000
+#define AR5K_PHY_ERR_FIL_CCK 0x02000000
+
+/*
+ * Rate duration register
+ */
+#define AR5K_RATE_DUR_BASE 0x8700
+#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))
+
+/*===5212===*/
+
+/*
+ * Key table (WEP) register
+ */
+#define AR5K_KEYTABLE_0_5210 0x9000
+#define AR5K_KEYTABLE_0_5211 0x8800
+#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
+#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) * 32))
+#define AR5K_KEYTABLE(_n) (hal->ah_version == AR5K_AR5210
? \
+ AR5K_KEYTABLE_5210(_n) :
AR5K_KEYTABLE_5211(_n))
+#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2))
+#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5)
+#define AR5K_KEYTABLE_TYPE_40 0x00000000
+#define AR5K_KEYTABLE_TYPE_104 0x00000001
+#define AR5K_KEYTABLE_TYPE_128 0x00000003
+#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /*5212*/
+#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /*!5210*/
+#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /*5212*/
+#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /*!5210*/
+#define AR5K_KEYTABLE_ANTENNA 0x00000008 /*5212*/
+#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6)
+#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7)
+#define AR5K_KEYTABLE_VALID 0x00008000
+
+#define AR5K_KEYTABLE_SIZE_5210 64
+#define AR5K_KEYTABLE_SIZE_5211 128
+#define AR5K_KEYTABLE_SIZE (hal->ah_version == AR5K_AR5210
? \
+ AR5K_KEYTABLE_SIZE_5210 :
AR5K_KEYTABLE_SIZE_5211)
+#define AR5K_KEYCACHE_SIZE 8
+
+
+
+/*===PHY REGISTERS===*/
+
+/*
+ * PHY register
+ */
+#define AR5K_PHY_BASE 0x9800
+#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
+#define AR5K_PHY_SHIFT_2GHZ 0x00004007
+#define AR5K_PHY_SHIFT_5GHZ 0x00000007
+
+/*
+ * PHY frame control register (5210) /turbo mode register (5211/5212)
+ *
+ * There is another frame control register for 5211/5212
+ * at address 0x9944 (see below) but the 2 first flags
+ * are common here between 5210 frame control register
+ * and 5211/5212 turbo mode register, so this also works as
+ * a "turbo mode register" for 5210. We treat this one as
+ * a frame control register for 5210 below.
+ */
+#define AR5K_PHY_TURBO 0x9804
+#define AR5K_PHY_TURBO_MODE 0x00000001
+#define AR5K_PHY_TURBO_SHORT 0x00000002
+
+/*
+ * PHY agility command register
+ */
+#define AR5K_PHY_AGC 0x9808
+#define AR5K_PHY_AGC_DISABLE 0x08000000
+
+/*
+ * PHY timing register (5212)
+ */
+#define AR5K_PHY_TIMING_3 0x9814
+#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
+#define AR5K_PHY_TIMING_3_DSC_MAN_S 17
+#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000
+#define AR5K_PHY_TIMING_3_DSC_EXP_S 13
+
+/*
+ * PHY chip revision register
+ */
+#define AR5K_PHY_CHIP_ID 0x9818
+
+/*
+ * PHY activation register
+ */
+#define AR5K_PHY_ACT 0x981c
+#define AR5K_PHY_ACT_ENABLE 0x00000001
+#define AR5K_PHY_ACT_DISABLE 0x00000002
+
+/*
+ * PHY signal register (5210)
+ */
+#define AR5K_PHY_SIG 0x9858
+#define AR5K_PHY_SIG_FIRSTEP 0x0003f000
+#define AR5K_PHY_SIG_FIRSTEP_S 12
+#define AR5K_PHY_SIG_FIRPWR 0x03fc0000
+#define AR5K_PHY_SIG_FIRPWR_S 18
+
+/*
+ * PHY coarse agility control register (5210)
+ */
+#define AR5K_PHY_AGCCOARSE 0x985c
+#define AR5K_PHY_AGCCOARSE_LO 0x00007f80
+#define AR5K_PHY_AGCCOARSE_LO_S 7
+#define AR5K_PHY_AGCCOARSE_HI 0x003f8000
+#define AR5K_PHY_AGCCOARSE_HI_S 15
+
+/*
+ * PHY agility control register
+ */
+#define AR5K_PHY_AGCCTL 0x9860
+#define AR5K_PHY_AGCCTL_CAL 0x00000001
+#define AR5K_PHY_AGCCTL_NF 0x00000002
+
+/*
+ * PHY noise floor status register
+ */
+#define AR5K_PHY_NF 0x9864
+#define AR5K_PHY_NF_M 0x000001ff
+#define AR5K_PHY_NF_ACTIVE 0x00000100
+#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M)
+#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1)
+#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
+
+/*
+ * PHY ADC saturation register (5210)
+ */
+#define AR5K_PHY_ADCSAT 0x9868
+#define AR5K_PHY_ADCSAT_ICNT 0x0001f800
+#define AR5K_PHY_ADCSAT_ICNT_S 11
+#define AR5K_PHY_ADCSAT_THR 0x000007e0
+#define AR5K_PHY_ADCSAT_THR_S 5
+
+/*
+ * PHY sleep registers (5212)
+ */
+#define AR5K_PHY_SCR 0x9870
+#define AR5K_PHY_SCR_32MHZ 0x0000001f
+#define AR5K_PHY_SLMT 0x9874
+#define AR5K_PHY_SLMT_32MHZ 0x0000007f
+#define AR5K_PHY_SCAL 0x9878
+#define AR5K_PHY_SCAL_32MHZ 0x0000000e
+
+/*
+ * PHY PLL control register (!5210)
+ */
+#define AR5K_PHY_PLL 0x987c
+#define AR5K_PHY_PLL_20MHZ 0x13 /*5211 only*/
+#define AR5K_PHY_PLL_40MHZ_5211 0x18
+#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
+#define AR5K_PHY_PLL_40MHZ (hal->ah_version == AR5K_AR5211
? \
+ AR5K_PHY_PLL_40MHZ_5211 :
AR5K_PHY_PLL_40MHZ_5212)
+#define AR5K_PHY_PLL_44MHZ_5211 0x19
+#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
+#define AR5K_PHY_PLL_44MHZ (hal->ah_version == AR5K_AR5211
? \
+ AR5K_PHY_PLL_44MHZ_5211 :
AR5K_PHY_PLL_44MHZ_5212)
+#define AR5K_PHY_PLL_AR5111 0x00000000
+#define AR5K_PHY_PLL_AR5112 0x00000040
+
+/*
+ * PHY RF stage register (5210)
+ */
+#define AR5K_PHY_RFSTG 0x98d4
+#define AR5K_PHY_RFSTG_DISABLE 0x00000021
+
+/*
+ * PHY receiver delay register (!5210)
+ */
+#define AR5K_PHY_RX_DELAY 0x9914
+#define AR5K_PHY_RX_DELAY_M 0x00003fff
+
+/*
+ * PHY timing IQ control register (!5210)
+ */
+#define AR5K_PHY_IQ 0x9920
+#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
+#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0
+#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5
+#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800
+#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
+#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12
+#define AR5K_PHY_IQ_RUN 0x00010000
+
+
+/*
+ * PHY PAPD probe register (!5210)
+ */
+#define AR5K_PHY_PAPD_PROBE 0x9930
+#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
+#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9
+#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
+#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /*5212 only*/
+#define AR5K_PHY_PAPD_PROBE_TYPE_S 23
+#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
+#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1
+#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2
+#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000
+#define AR5K_PHY_PAPD_PROBE_GAINF_S 25
+
+
+/*
+ * PHY TX power registers (5212)
+ */
+#define AR5K_PHY_TXPOWER_RATE1 0x9934
+#define AR5K_PHY_TXPOWER_RATE2 0x9938
+#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c
+#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
+#define AR5K_PHY_TXPOWER_RATE3 0xa234
+#define AR5K_PHY_TXPOWER_RATE4 0xa238
+
+/*
+ * PHY frame control register (!5210)
+ */
+#define AR5K_PHY_FRAME_CTL_5210 0x9804
+#define AR5K_PHY_FRAME_CTL_5211 0x9944
+#define AR5K_PHY_FRAME_CTL (hal->ah_version == AR5K_AR5210
? \
+ AR5K_PHY_FRAME_CTL_5210 :
AR5K_PHY_FRAME_CTL_5211)
+/*---non 5210---*/
+#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038
+#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
+/*---5210 only---*/
+#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000
+#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000
+#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000
+#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000
+#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
+#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000
+
+/*
+ * PHY radar detection enable register (!5210)
+ */
+#define AR5K_PHY_RADAR 0x9954
+#define AR5K_PHY_RADAR_DISABLE 0x00000000
+#define AR5K_PHY_RADAR_ENABLE 0x00000001
+
+/*
+ * PHY antenna switch table registers (!5210)
+ */
+#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
+#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
+
+/*
+ * PHY clock sleep registers (5212)
+ */
+#define AR5K_PHY_SCLOCK 0x99f0
+#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
+#define AR5K_PHY_SDELAY 0x99f4
+#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
+#define AR5K_PHY_SPENDING 0x99f8
+#define AR5K_PHY_SPENDING_AR5111 0x00000018
+#define AR5K_PHY_SPENDING_AR5112 0x00000014
+
+/*
+ * Misc PHY/radio registers (5210/5211)
+ */
+#define AR5K_BB_GAIN_BASE 0x9b00
+#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
+#define AR5K_RF_GAIN_BASE 0x9a00
+#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
+
+/*
+ * PHY timing IQ calibration result register (!5210)
+ */
+#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10
+#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14
+#define AR5K_PHY_IQRES_CAL_CORR 0x9c18
+
+/*
+ * PHY current RSSI register (!5210)
+ */
+#define AR5K_PHY_CURRENT_RSSI 0x9c1c
+
+/*
+ * PHY PCDAC TX power register (5212)
+ */
+#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
+#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE +
((_n) << 2))
+
+/*
+ * PHY mode register (!5210)
+ */
+#define AR5K_PHY_MODE 0x0a200
+#define AR5K_PHY_MODE_MOD 0x00000001
+#define AR5K_PHY_MODE_MOD_OFDM 0
+#define AR5K_PHY_MODE_MOD_CCK 1
+#define AR5K_PHY_MODE_FREQ 0x00000002
+#define AR5K_PHY_MODE_FREQ_5GHZ 0
+#define AR5K_PHY_MODE_FREQ_2GHZ 2
+#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /*5212 only*/
+#define AR5K_PHY_MODE_RAD 0x00000008 /*5212 only*/
+#define AR5K_PHY_MODE_RAD_AR5111 0
+#define AR5K_PHY_MODE_RAD_AR5112 8
+#define AR5K_PHY_MODE_XR 0x00000010 /*5212 only*/
+
+/*
+ * PHY CCK transmit control register (5212)
+ */
+#define AR5K_PHY_CCKTXCTL 0xa204
+#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
+#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
+
+/*
+ * PHY 2GHz gain register (5212)
+ */
+#define AR5K_PHY_GAIN_2GHZ 0xa20c
+#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
+#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation, Clemens Kolbitsch, 2008/03/18
- [Qemu-devel] Re: Re: Re: Atheros Wireless Device Emulation,
Clemens Kolbitsch <=