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Re: [Qemu-devel] [PATCH 4/4] target-arm: neon fix
From: |
Laurent Desnogues |
Subject: |
Re: [Qemu-devel] [PATCH 4/4] target-arm: neon fix |
Date: |
Sun, 7 Feb 2010 14:02:31 +0100 |
On Sun, Feb 7, 2010 at 1:54 PM, Laurent Desnogues
<address@hidden> wrote:
> On Fri, Feb 5, 2010 at 4:52 PM, Riku Voipio <address@hidden> wrote:
>> From: Juha Riihimäki <address@hidden>
>>
>> add an extra check in "two registers and a shift" to ensure element
>> size decoding logic cannot fail.
>>
>> Signed-off-by: Juha Riihimäki <address@hidden>
>> Signed-off-by: Riku Voipio <address@hidden>
>> ---
>> target-arm/translate.c | 3 ++-
>> 1 files changed, 2 insertions(+), 1 deletions(-)
>>
>> diff --git a/target-arm/translate.c b/target-arm/translate.c
>> index 743b846..8bba034 100644
>> --- a/target-arm/translate.c
>> +++ b/target-arm/translate.c
>> @@ -4567,8 +4567,9 @@ static int disas_neon_data_insn(CPUState * env,
>> DisasContext *s, uint32_t insn)
>> size = 3;
>> } else {
>> size = 2;
>> - while (size && (insn & (1 << (size + 19))) == 0)
>> + while (size && (insn & (1 << (size + 19))) == 0) {
>> size--;
>> + }
>> }
>> shift = (insn >> 16) & ((1 << (3 + size)) - 1);
>> /* To avoid excessive dumplication of ops we implement shift
>
> I think there's a patch ordering problem that makes
> the comment and the change not agree :-)
BTW I don't think adding the check for size is needed
here. The encoding at that point looks like this:
3322222222221111111111
10987654321098765432109876543210
1111001_1___1______________1____
1111001_1__1_______________1____
1111001_1_1________________1____
so it will stop for size == 0 given that bit 19 will have to
be set.
Laurent
[Qemu-devel] [PATCH 1/4] target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN, Riku Voipio, 2010/02/05
[Qemu-devel] [PATCH 2/4] target-arm: neon vshll instruction fix, Riku Voipio, 2010/02/05
[Qemu-devel] [PATCH 3/4] target-arm: neon emulation enhancements, Riku Voipio, 2010/02/05