[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 5/7] target-arm: Translate with condexec bits from T
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 5/7] target-arm: Translate with condexec bits from TB flags, not CPUState |
Date: |
Fri, 7 Jan 2011 15:06:32 +0000 |
When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.
This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT
block, because when we came to retranslate in cpu_restore_state()
the CPUState condexec bits would have advanced compared to the start
of the TB and we would generate different (wrong) code.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 723961a..7d042ee 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9075,8 +9075,8 @@ static inline void
gen_intermediate_code_internal(CPUState *env,
dc->singlestep_enabled = env->singlestep_enabled;
dc->condjmp = 0;
dc->thumb = tb->flags & 1;
- dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
- dc->condexec_cond = env->condexec_bits >> 4;
+ dc->condexec_mask = (tb->flags & 0xf00) >> 7;
+ dc->condexec_cond = (tb->flags & 0xf000) >> 12;
#if !defined(CONFIG_USER_ONLY)
if (IS_M(env)) {
dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
@@ -9105,7 +9105,7 @@ static inline void
gen_intermediate_code_internal(CPUState *env,
gen_icount_start();
/* Reset the conditional execution bits immediately. This avoids
complications trying to do it at the end of the block. */
- if (env->condexec_bits)
+ if (dc->condexec_mask || dc->condexec_cond)
{
TCGv tmp = new_tmp();
tcg_gen_movi_i32(tmp, 0);
--
1.6.3.3
- [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 6/7] target-arm: Set privileged bit in TB flags correctly for M profile, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 3/7] target-arm: Translate with VFP len/stride from TB flags, not CPUState, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 2/7] target-arm: Translate with VFP-enabled from TB flags, not CPUState, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 4/7] target-arm: Translate with Thumb state from TB flags, not CPUState, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 1/7] target-arm: Don't generate code specific to current CPU mode for SRS, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 5/7] target-arm: Translate with condexec bits from TB flags, not CPUState,
Peter Maydell <=
- [Qemu-devel] [PATCH 7/7] target-arm: Translate with user-state from TB flags, not CPUState, Peter Maydell, 2011/01/07
- Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState, Aurelien Jarno, 2011/01/07