[Qemu-devel] [PATCH V2 2/7] hw/acpi_piix4.c: replace register_ioport*

[Julien Grall]

This patch replaces all register_ioport* with portio_*. It permits to
use the new Memory stuff like listener.

Signed-off-by: Julien Grall <address@hidden>
---
 hw/acpi_piix4.c |   76 +++++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 65 insertions(+), 11 deletions(-)

diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 797ed24..b9b195b 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -61,6 +61,13 @@ typedef struct PIIX4PMState {
     PMSMBus smb;
     uint32_t smb_io_base;
 
+    PortioList port_list;
+    PortioList acpi_port_list;
+    PortioList acpi_hot_port_list;
+    PortioList pci_hot_port_list;
+    PortioList pciej_hot_port_list;
+    PortioList pcirmv_hot_port_list;
+
     qemu_irq irq;
     qemu_irq smi_irq;
     int kvm_enabled;
@@ -325,6 +332,17 @@ static void piix4_pm_machine_ready(Notifier *n, void 
*opaque)
 
 }
 
+static const MemoryRegionPortio piix4_portio_list[] = {
+    { 0x00, 64, 1, .read = smb_ioport_readb, }, /* s->smb_io_base */
+    { 0x00, 64, 1, .write = smb_ioport_writeb, }, /* s->smb_io_base */
+    PORTIO_END_OF_LIST(),
+};
+
+static const MemoryRegionPortio acpi_portio_list[] = {
+    { 0x00, 4, 4, .write = acpi_dbg_writel, }, /* ACPI_DBG_IO_ADDR */
+    PORTIO_END_OF_LIST(),
+};
+
 static int piix4_pm_initfn(PCIDevice *dev)
 {
     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
@@ -341,7 +359,9 @@ static int piix4_pm_initfn(PCIDevice *dev)
     /* APM */
     apm_init(&s->apm, apm_ctrl_changed, s);
 
-    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
+    portio_list_init(&s->acpi_port_list, acpi_portio_list, s, "piix4-acpi");
+    portio_list_add(&s->acpi_port_list, pci_address_space_io(dev),
+                    ACPI_DBG_IO_ADDR);
 
     if (s->kvm_enabled) {
         /* Mark SMM as already inited to prevent SMM from running.  KVM does 
not
@@ -354,8 +374,10 @@ static int piix4_pm_initfn(PCIDevice *dev)
     pci_conf[0x90] = s->smb_io_base | 1;
     pci_conf[0x91] = s->smb_io_base >> 8;
     pci_conf[0xd2] = 0x09;
-    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
-    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
+
+    portio_list_init(&s->port_list, piix4_portio_list, s, "piix4-acpi");
+    portio_list_add(&s->port_list, pci_address_space_io(dev),
+                    s->smb_io_base);
 
     acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
     acpi_gpe_init(&s->ar, GPE_LEN);
@@ -521,22 +543,54 @@ static void pcirmv_write(void *opaque, uint32_t addr, 
uint32_t val)
 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
                                 PCIHotplugState state);
 
+static const MemoryRegionPortio acpi_hot_portio_list[] = {
+    { 0x00, GPE_LEN, 1, .write = gpe_writeb,
+        .read = gpe_readb, }, /* GPE_BASE */
+    PORTIO_END_OF_LIST(),
+};
+
+/* IOport from PCI_BASE */
+static const MemoryRegionPortio pci_hot_portio_list[] = {
+    { 0x00, 8, 4, .write = pcihotplug_write, .read = pcihotplug_read, },
+    PORTIO_END_OF_LIST(),
+};
+
+/* IOport from PCI_EJ_BASE */
+static const MemoryRegionPortio pciej_hot_portio_list[] = {
+    { 0x00, 4, 4, .write = pciej_write, .read = pciej_read, },
+    PORTIO_END_OF_LIST(),
+};
+
+/* IOport form PCI_RMV_BASE */
+static const MemoryRegionPortio pcirmv_hot_portio_list[] = {
+    { 0x00, 4, 4, .write = pcirmv_write, .read = pcirmv_read, },
+    PORTIO_END_OF_LIST(),
+};
+
 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 {
     struct pci_status *pci0_status = &s->pci0_status;
 
-    register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
-    register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
+    portio_list_init(&s->acpi_hot_port_list, acpi_hot_portio_list,
+                     s, "piix4-acpi-hot");
+    portio_list_add(&s->acpi_hot_port_list, pci_address_space_io(&s->dev),
+                    GPE_BASE);
     acpi_gpe_blk(&s->ar, GPE_BASE);
 
-    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
-    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
+    portio_list_init(&s->pci_hot_port_list, pci_hot_portio_list,
+                     pci0_status, "piix4-pci-hot");
+    portio_list_add(&s->pci_hot_port_list, pci_address_space_io(&s->dev),
+                    PCI_BASE);
 
-    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
-    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
+    portio_list_init(&s->pciej_hot_port_list, pciej_hot_portio_list,
+                     bus, "piix4-pciej-hot");
+    portio_list_add(&s->pciej_hot_port_list, pci_address_space_io(&s->dev),
+                    PCI_EJ_BASE);
 
-    register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
-    register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
+    portio_list_init(&s->pcirmv_hot_port_list, pcirmv_hot_portio_list,
+                     s, "piix4-pcirmv-hot");
+    portio_list_add(&s->pcirmv_hot_port_list, pci_address_space_io(&s->dev),
+                    PCI_RMV_BASE);
 
     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 }
-- 
Julien Grall