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Re: [Qemu-devel] [PATCH 06/13] target-arm: A64: add support for 2-src sh
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 06/13] target-arm: A64: add support for 2-src shift reg insns |
Date: |
Fri, 06 Dec 2013 11:52:43 +1300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 |
On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf <address@hidden>
>
> This adds 2-src variable shift register instructions:
> C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
>
> Signed-off-by: Alexander Graf <address@hidden>
> [claudio: adapted to new decoder, use enums for shift types]
> Signed-off-by: Claudio Fontana <address@hidden>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate-a64.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
Reviewed-by: Richard Henderson <address@hidden>
r~
[Qemu-devel] [PATCH 12/13] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/05