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[Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and sou
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and source selection |
Date: |
Thu, 17 Apr 2014 11:33:58 +0100 |
From: Beniamino Galvani <address@hidden>
This implements the prescaler and source fields of the timer control
register. The source for each timer can be selected among 4 clock
inputs whose frequencies are set through model properties.
Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/cubieboard.c | 13 +++++++++++++
hw/timer/allwinner-a10-pit.c | 28 +++++++++++++++++++++++++++-
include/hw/timer/allwinner-a10-pit.h | 1 +
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index d95a7f3..9d158c7 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -43,6 +43,19 @@ static void cubieboard_init(QEMUMachineInitArgs *args)
exit(1);
}
+ object_property_set_int(OBJECT(&s->a10->timer), 32768, "clk0-freq", &err);
+ if (err != NULL) {
+ error_report("Couldn't set clk0 frequency: %s", error_get_pretty(err));
+ exit(1);
+ }
+
+ object_property_set_int(OBJECT(&s->a10->timer), 24000000, "clk1-freq",
+ &err);
+ if (err != NULL) {
+ error_report("Couldn't set clk1 frequency: %s", error_get_pretty(err));
+ exit(1);
+ }
+
object_property_set_bool(OBJECT(s->a10), true, "realized", &err);
if (err != NULL) {
error_report("Couldn't realize Allwinner A10: %s",
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index 5aa78a9..d3c02ea 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -74,6 +74,22 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset,
unsigned size)
return 0;
}
+static void a10_pit_set_freq(AwA10PITState *s, int index)
+{
+ uint32_t prescaler, source, source_freq;
+
+ prescaler = 1 << extract32(s->control[index], 4, 3);
+ source = extract32(s->control[index], 2, 2);
+ source_freq = s->clk_freq[source];
+
+ if (source_freq) {
+ ptimer_set_freq(s->timer[index], source_freq / prescaler);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n",
+ __func__, source);
+ }
+}
+
static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
@@ -96,6 +112,7 @@ static void a10_pit_write(void *opaque, hwaddr offset,
uint64_t value,
switch (offset & 0x0f) {
case AW_A10_PIT_TIMER_CONTROL:
s->control[index] = value;
+ a10_pit_set_freq(s, index);
if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
ptimer_set_count(s->timer[index], s->interval[index]);
}
@@ -161,6 +178,14 @@ static const MemoryRegionOps a10_pit_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static Property a10_pit_properties[] = {
+ DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
+ DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
+ DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
+ DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static const VMStateDescription vmstate_a10_pit = {
.name = "a10.pit",
.version_id = 1,
@@ -196,6 +221,7 @@ static void a10_pit_reset(DeviceState *dev)
s->interval[i] = 0;
s->count[i] = 0;
ptimer_stop(s->timer[i]);
+ a10_pit_set_freq(s, i);
}
s->watch_dog_mode = 0;
s->watch_dog_control = 0;
@@ -241,7 +267,6 @@ static void a10_pit_init(Object *obj)
tc->index = i;
bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
s->timer[i] = ptimer_init(bh[i]);
- ptimer_set_freq(s->timer[i], 240000);
}
}
@@ -250,6 +275,7 @@ static void a10_pit_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = a10_pit_reset;
+ dc->props = a10_pit_properties;
dc->desc = "allwinner a10 timer";
dc->vmsd = &vmstate_a10_pit;
}
diff --git a/include/hw/timer/allwinner-a10-pit.h
b/include/hw/timer/allwinner-a10-pit.h
index a48d3c7..f759ba5 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -50,6 +50,7 @@ typedef struct AwA10PITState {
ptimer_state * timer[AW_A10_PIT_TIMER_NR];
AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
MemoryRegion iomem;
+ uint32_t clk_freq[4];
uint32_t irq_enable;
uint32_t irq_status;
--
1.9.1
- [Qemu-devel] [PULL 00/51] target-arm queue, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 48/51] misc: zynq_slcr: Make DB_PRINTs always compile, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 49/51] net: cadence_gem: Make phy respond to broadcast, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 47/51] misc: zynq_slcr: Convert SBD::init to object init, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 50/51] arm: translate.c: Fix smlald Instruction, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 51/51] target-arm: A64: fix unallocated test of scalar SQXTUN, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 44/51] allwinner-emac: set autonegotiation complete bit on link up, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and source selection,
Peter Maydell <=
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 42/51] allwinner-a10-pit: use level triggered interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 01/51] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 39/51] allwinner-a10-pic: set vector address when an interrupt is pending, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 46/51] misc: zynq-slcr: Rewrite, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 38/51] timer: cadence_ttc: Fix match register write logic, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 34/51] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/17