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Re: [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spu
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts |
Date: |
Thu, 17 Apr 2014 21:40:40 +0100 |
On 17 April 2014 11:33, Peter Maydell <address@hidden> wrote:
> From: Beniamino Galvani <address@hidden>
> diff --git a/include/hw/timer/allwinner-a10-pit.h
> b/include/hw/timer/allwinner-a10-pit.h
> index 15efab8..a48d3c7 100644
> --- a/include/hw/timer/allwinner-a10-pit.h
> +++ b/include/hw/timer/allwinner-a10-pit.h
> @@ -35,12 +35,20 @@
>
> #define AW_A10_PIT_DEFAULT_CLOCK 0x4
>
> +typedef struct AwA10PITState AwA10PITState;
> +
> +typedef struct AwA10TimerContext {
> + AwA10PITState *container;
> + int index;
> +} AwA10TimerContext;
> +
> typedef struct AwA10PITState {
> /*< private >*/
> SysBusDevice parent_obj;
> /*< public >*/
> qemu_irq irq[AW_A10_PIT_TIMER_NR];
> ptimer_state * timer[AW_A10_PIT_TIMER_NR];
> + AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
> MemoryRegion iomem;
>
> uint32_t irq_enable;
> --
This turns out to not compile on the mingw32 compiler
(perhaps just because it's a newer gcc?) -- it's pickier
about the fact we've defined this typedef twice. I've applied
the following fixup to the patch and regenerated the
pull request:
cam-vm-266:precise:qemu$ git diff
diff --git a/include/hw/timer/allwinner-a10-pit.h
b/include/hw/timer/allwinner-a10-pit.h
index a48d3c7..2158fc0 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -42,7 +42,7 @@ typedef struct AwA10TimerContext {
int index;
} AwA10TimerContext;
-typedef struct AwA10PITState {
+struct AwA10PITState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@@ -61,6 +61,6 @@ typedef struct AwA10PITState {
uint32_t count_lo;
uint32_t count_hi;
uint32_t count_ctl;
-} AwA10PITState;
+};
#endif
(not resending in the interests of avoiding spamming
the list with 50 patches again...)
thanks
-- PMM
- [Qemu-devel] [PULL 00/51] target-arm queue, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 48/51] misc: zynq_slcr: Make DB_PRINTs always compile, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 49/51] net: cadence_gem: Make phy respond to broadcast, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 47/51] misc: zynq_slcr: Convert SBD::init to object init, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 50/51] arm: translate.c: Fix smlald Instruction, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 51/51] target-arm: A64: fix unallocated test of scalar SQXTUN, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 44/51] allwinner-emac: set autonegotiation complete bit on link up, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and source selection, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts, Peter Maydell, 2014/04/17
- Re: [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts,
Peter Maydell <=
- [Qemu-devel] [PULL 42/51] allwinner-a10-pit: use level triggered interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 01/51] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 39/51] allwinner-a10-pic: set vector address when an interrupt is pending, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 46/51] misc: zynq-slcr: Rewrite, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 38/51] timer: cadence_ttc: Fix match register write logic, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 34/51] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/17