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From: | Pierre Mallard |
Subject: | Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs |
Date: | Thu, 11 Sep 2014 00:43:59 +0200 |
(1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer Conversion instructions.
(2) Defined a new flag for FP Signed Doubleword Conversion instructions (PPC2_FP_CVT_S64). Use this flag exclusively when defining the opcode tables, e.g.
+/* fctidz */
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
(3) You would have to add the flag to all existing 64-bit CPUs that support floating point. And of course, to your new 440-w-fpu CPU.
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