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[Qemu-devel] [PULL 12/17] target-arm: Add user-mode transaction attribut
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/17] target-arm: Add user-mode transaction attribute |
Date: |
Mon, 27 Apr 2015 16:20:40 +0100 |
Add a transaction attribute indicating that a memory access is being
done from user-mode (unprivileged). This corresponds to an equivalent
signal in ARM AMBA buses.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
include/exec/memattrs.h | 2 ++
target-arm/helper.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 68a9c76..1389b4b 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -31,6 +31,8 @@ typedef struct MemTxAttrs {
unsigned int unspecified:1;
/* ARM/AMBA TrustZone Secure access */
unsigned int secure:1;
+ /* Memory access is usermode (unprivileged) */
+ unsigned int user:1;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a01ff7f..50469cd 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5749,6 +5749,7 @@ static inline int get_phys_addr(CPUARMState *env,
target_ulong address,
* to secure.
*/
attrs->secure = regime_is_secure(env, mmu_idx);
+ attrs->user = regime_is_user(env, mmu_idx);
/* Fast Context Switch Extension. This doesn't exist at all in v8.
* In v7 and earlier it affects all stage 1 translations.
--
1.9.1
- [Qemu-devel] [PULL 00/17] target-arm queue, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 17/17] Allow ARMv8 SCR.SMD updates, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 14/17] target-arm: Check watchpoints against CPU security state, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 16/17] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 01/17] memory: Define API for MemoryRegionOps to take attrs and return status, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 15/17] target-arm: rename c1_coproc to cpacr_el1, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 12/17] target-arm: Add user-mode transaction attribute,
Peter Maydell <=
- [Qemu-devel] [PULL 13/17] target-arm: Use attribute info to handle user-only watchpoints, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 11/17] target-arm: Use correct memory attributes for page table walks, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 10/17] target-arm: Honour NS bits in page tables, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 05/17] exec.c: Convert subpage memory ops to _with_attrs, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 03/17] Make CPU iotlb a structure rather than a plain hwaddr, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 06/17] exec.c: Make address_space_rw take transaction attributes, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 07/17] exec.c: Add new address_space_ld*/st* functions, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 09/17] Switch non-CPU callers from ld/st*_phys to address_space_ld/st*, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 02/17] memory: Replace io_mem_read/write with memory_region_dispatch_read/write, Peter Maydell, 2015/04/27
- [Qemu-devel] [PULL 08/17] exec.c: Capture the memory attributes for a watchpoint hit, Peter Maydell, 2015/04/27