[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 5/7] hw/intc/arm_gic_common.c: Reset all registers
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 5/7] hw/intc/arm_gic_common.c: Reset all registers |
Date: |
Mon, 6 Jul 2015 10:59:33 +0100 |
The arm_gic_common reset function was missing reset code for
several of the GIC's state fields:
* bpr[]
* abpr[]
* priority1[]
* priority2[]
* sgi_pending[]
* irq_target[] (SMP configurations only)
These probably went unnoticed because most guests will either
never touch them, or will write to them in the process of
configuring the GIC before enabling interrupts.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
hw/intc/arm_gic_common.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index 044ad66..a64d071 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -123,7 +123,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error
**errp)
static void arm_gic_common_reset(DeviceState *dev)
{
GICState *s = ARM_GIC_COMMON(dev);
- int i;
+ int i, j;
memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
for (i = 0 ; i < s->num_cpu; i++) {
if (s->revision == REV_11MPCORE) {
@@ -135,15 +135,30 @@ static void arm_gic_common_reset(DeviceState *dev)
s->running_irq[i] = 1023;
s->running_priority[i] = 0x100;
s->cpu_ctlr[i] = 0;
+ s->bpr[i] = GIC_MIN_BPR;
+ s->abpr[i] = GIC_MIN_ABPR;
+ for (j = 0; j < GIC_INTERNAL; j++) {
+ s->priority1[j][i] = 0;
+ }
+ for (j = 0; j < GIC_NR_SGIS; j++) {
+ s->sgi_pending[j][i] = 0;
+ }
}
for (i = 0; i < GIC_NR_SGIS; i++) {
GIC_SET_ENABLED(i, ALL_CPU_MASK);
GIC_SET_EDGE_TRIGGER(i);
}
- if (s->num_cpu == 1) {
+
+ for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
+ s->priority2[i] = 0;
+ }
+
+ for (i = 0; i < GIC_MAXIRQ; i++) {
/* For uniprocessor GICs all interrupts always target the sole CPU */
- for (i = 0; i < GIC_MAXIRQ; i++) {
+ if (s->num_cpu == 1) {
s->irq_target[i] = 1;
+ } else {
+ s->irq_target[i] = 0;
}
}
s->ctlr = 0;
--
1.9.1
- [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 5/7] hw/intc/arm_gic_common.c: Reset all registers,
Peter Maydell <=
- [Qemu-devel] [PULL 3/7] target-arm: Split DISAS_YIELD from DISAS_WFE, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 1/7] target-arm: fix write helper for TLBI ALLE1IS, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 7/7] arm_mptimer: Respect IT bit state, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 6/7] arm_mptimer: Fix timer shutdown and mode change, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 4/7] target-arm: Implement YIELD insn to yield in ARM and Thumb translators, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 2/7] Fix interval interrupt of cadence ttc when timer is in decrement mode, Peter Maydell, 2015/07/06
- Re: [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/07/06