Re: [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL

[Peter Maydell]

On 2 September 2015 at 18:57, Richard Henderson <address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target-arm/translate-a64.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index 74dd0f8..8c94edf 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -3020,6 +3020,23 @@ static void disas_bitfield(DisasContext *s, uint32_t 
> insn)
>              tcg_gen_sari_i64(tcg_rd, tcg_tmp, ri);
>              goto done;
>          }
> +    } else if (opc == 2) { /* UBFM */
> +        if (ri == 0) { /* UXTB, UXTH, plus non-canonical AND */
> +            tcg_gen_andi_i64(tcg_rd, tcg_tmp, bitmask64(si + 1));
> +            return;
> +        }
> +        if (si == 63 || (si == 31 && ri <= si)) { /* LSR */
> +            if (si == 31) {
> +                tcg_gen_ext32u_i64(tcg_tmp, tcg_tmp);
> +            }
> +            tcg_gen_shri_i64(tcg_rd, tcg_tmp, ri);
> +            return;
> +        }
> +        if (si + 1 == ri && si != bitsize - 1) { /* LSL */
> +            int shift = bitsize - 1 - si;
> +            tcg_gen_shli_i64(tcg_rd, tcg_tmp, shift);
> +            goto done;
> +        }
>      }
>
>      if (opc != 1) { /* SBFM or UBFM */

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM