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[Qemu-devel] [PATCH v4 08/13] target-arm: Avoid inline for get_phys_addr
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v4 08/13] target-arm: Avoid inline for get_phys_addr |
Date: |
Thu, 15 Oct 2015 00:55:41 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Avoid inline for get_phys_addr() to prepare for future recursive use.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d1ffcdf..17d0590 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -15,10 +15,10 @@
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
#ifndef CONFIG_USER_ONLY
-static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
- int access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int
*prot,
- target_ulong *page_size, uint32_t *fsr);
+static bool get_phys_addr(CPUARMState *env, target_ulong address,
+ int access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
+ target_ulong *page_size, uint32_t *fsr);
/* Definitions for the PMCCNTR and PMCR registers */
#define PMCRD 0x8
@@ -7059,10 +7059,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t address,
* @page_size: set to the size of the page containing phys_ptr
* @fsr: set to the DFSR/IFSR value on failure
*/
-static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
- int access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int
*prot,
- target_ulong *page_size, uint32_t *fsr)
+static bool get_phys_addr(CPUARMState *env, target_ulong address,
+ int access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
+ target_ulong *page_size, uint32_t *fsr)
{
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
/* TODO: when we support EL2 we should here call ourselves recursively
--
1.9.1
- Re: [Qemu-devel] [PATCH v4 11/13] target-arm: Add S2 translation to 32bit S1 PTWs, (continued)
- [Qemu-devel] [PATCH v4 12/13] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 09/13] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 10/13] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 07/13] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 08/13] target-arm: Avoid inline for get_phys_addr,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v4 13/13] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 05/13] target-arm: lpae: Rename granule_sz to stride, Edgar E. Iglesias, 2015/10/15
- [Qemu-devel] [PATCH v4 06/13] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/10/15