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[Qemu-devel] [PULL 03/13] target-arm: Avoid calling arm_el_is_aa64() fun
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/13] target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL |
Date: |
Fri, 16 Oct 2015 14:57:57 +0100 |
From: Sergey Sorokin <address@hidden>
It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
This patch fixes several attempts to do so.
Signed-off-by: Sergey Sorokin <address@hidden>
[PMM: Reworked several of the comments to be more verbose.]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 11 ++++++++---
target-arm/helper.c | 15 +++++++++++++--
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 493f9d0..5fb0479 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1016,11 +1016,11 @@ static inline bool access_secure_reg(CPUARMState *env)
*/
#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
A32_BANKED_REG_GET((_env), _regname, \
- ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
+ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)
\
A32_BANKED_REG_SET((_env), _regname, \
- ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))),
\
+ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
(_val))
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@@ -1587,7 +1587,12 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
* interrupt.
*/
if ((target_el > cur_el) && (target_el != 1)) {
- if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) {
+ /* ARM_FEATURE_AARCH64 enabled means the highest EL is AArch64.
+ * This code currently assumes that EL2 is not implemented
+ * (and so that highest EL will be 3 and the target_el also 3).
+ */
+ if (arm_feature(env, ARM_FEATURE_AARCH64) ||
+ ((scr || hcr) && (!secure))) {
unmasked = 1;
}
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b498670..b2d78b0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5224,11 +5224,22 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t
excp_idx,
uint32_t cur_el, bool secure)
{
CPUARMState *env = cs->env_ptr;
- int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
+ int rw;
int scr;
int hcr;
int target_el;
- int is64 = arm_el_is_aa64(env, 3);
+ /* Is the highest EL AArch64? */
+ int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
+
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
+ } else {
+ /* Either EL2 is the highest EL (and so the EL2 register width
+ * is given by is64); or there is no EL2 or EL3, in which case
+ * the value of 'rw' does not affect the table lookup anyway.
+ */
+ rw = is64;
+ }
switch (excp_idx) {
case EXCP_IRQ:
--
1.9.1
- [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 03/13] target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL,
Peter Maydell <=
- [Qemu-devel] [PULL 02/13] target-arm: Break the TB after ISB to execute self-modified code correctly, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 12/13] target-arm: Fix GDB breakpoint handling, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 10/13] hw/arm/virt: Allow zero address for PCI IO space, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 09/13] target-arm: Add MDCR_EL2, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 07/13] arm: imx25-pdk: Fix machine name, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 13/13] target-arm: Fix CPU breakpoint handling, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 11/13] target-arm: implement arm_debug_target_el(), Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 08/13] misc: zynq_slcr: Fix MMIO writes, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 01/13] target-arm: Add missing 'static' attribute, Peter Maydell, 2015/10/16