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[Qemu-devel] [PULL 09/13] target-arm: Add MDCR_EL2
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/13] target-arm: Add MDCR_EL2 |
Date: |
Fri, 16 Oct 2015 14:58:03 +0100 |
From: Sergey Fedorov <address@hidden>
Add the MDCR_EL2 register. We don't implement any of
the debug-related traps this register controls yet, so
currently it simply reads back as written.
Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: tweaked commit message; moved non-dummy definition from
debug_cp_reginfo to el2_cp_reginfo.]
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d1b5bc1..e555122 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -380,6 +380,7 @@ typedef struct CPUARMState {
uint64_t dbgwcr[16]; /* watchpoint control registers */
uint64_t mdscr_el1;
uint64_t oslsr_el1; /* OS Lock Status */
+ uint64_t mdcr_el2;
/* If the counter is enabled, this stores the last time the counter
* was reset. Otherwise it stores the counter value
*/
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 403a30e..e7fda37 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3227,6 +3227,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
@@ -3448,6 +3451,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0,
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
#endif
+ /* The only field of MDCR_EL2 that has a defined architectural reset value
+ * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
+ * don't impelment any PMU event counters, so using zero as a reset
+ * value for MDCR_EL2 is okay
+ */
+ { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
+ .access = PL2_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
REGINFO_SENTINEL
};
--
1.9.1
- [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 03/13] target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 02/13] target-arm: Break the TB after ISB to execute self-modified code correctly, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 12/13] target-arm: Fix GDB breakpoint handling, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 10/13] hw/arm/virt: Allow zero address for PCI IO space, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 09/13] target-arm: Add MDCR_EL2,
Peter Maydell <=
- [Qemu-devel] [PULL 07/13] arm: imx25-pdk: Fix machine name, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 13/13] target-arm: Fix CPU breakpoint handling, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 11/13] target-arm: implement arm_debug_target_el(), Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 08/13] misc: zynq_slcr: Fix MMIO writes, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 01/13] target-arm: Add missing 'static' attribute, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 06/13] target-arm: Provide model numbers for Sharp PDAs, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 04/13] hw/arm/virt: smbios: inform guest of kvm, Peter Maydell, 2015/10/16
- [Qemu-devel] [PULL 05/13] target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs, Peter Maydell, 2015/10/16
- Re: [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2015/10/17