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[Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing NSACR.RFR |
Date: |
Fri, 26 Feb 2016 15:20:11 +0000 |
QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b2d2440..57cc879 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5214,6 +5214,9 @@ static int bad_mode_switch(CPUARMState *env, int mode)
case ARM_CPU_MODE_UND:
case ARM_CPU_MODE_IRQ:
case ARM_CPU_MODE_FIQ:
+ /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
+ * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
+ */
return 0;
case ARM_CPU_MODE_MON:
return !arm_is_secure(env);
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing NSACR.RFR,
Peter Maydell <=
- [Qemu-devel] [PULL 01/20] target-arm: Give CPSR setting on 32-bit exception return its own helper, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 03/20] target-arm: Raw CPSR writes should skip checks and bank switching, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 10/20] target-arm: Make mode switches from Hyp via CPS and MRS illegal, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 05/20] target-arm: In cpsr_write() ignore mode switches from User mode, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 08/20] target-arm: Forbid mode switch to Mon from Secure EL1, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 02/20] target-arm: Add write_type argument to cpsr_write(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 17/20] sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts", Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 12/20] target-arm: Fix handling of SDCR for 32-bit code, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 04/20] linux-user: Use restrictive mask when calling cpsr_write(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 11/20] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1, Peter Maydell, 2016/02/26