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[Qemu-devel] [PATCH 08/52] target-m68k: define operand sizes
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 08/52] target-m68k: define operand sizes |
Date: |
Wed, 4 May 2016 22:11:48 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/cpu.h | 8 ++++++++
target-m68k/translate.c | 46 ++++++++++++++--------------------------------
2 files changed, 22 insertions(+), 32 deletions(-)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 2b79f26..e788684 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -29,6 +29,14 @@
#include "fpu/softfloat.h"
+#define OS_BYTE 0
+#define OS_WORD 1
+#define OS_LONG 2
+#define OS_SINGLE 3
+#define OS_DOUBLE 4
+#define OS_EXTENDED 5
+#define OS_PACKED 6
+
#define MAX_QREGS 32
#define EXCP_ACCESS 2 /* Access (MMU) error. */
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index e2555f6..0da0dff 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -152,12 +152,6 @@ typedef struct DisasContext {
static void *gen_throws_exception;
#define gen_last_qop NULL
-#define OS_BYTE 0
-#define OS_WORD 1
-#define OS_LONG 2
-#define OS_SINGLE 4
-#define OS_DOUBLE 5
-
typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
#ifdef DEBUG_DISPATCH
@@ -451,11 +445,23 @@ static inline int opsize_bytes(int opsize)
case OS_LONG: return 4;
case OS_SINGLE: return 4;
case OS_DOUBLE: return 8;
+ case OS_EXTENDED: return 12;
+ case OS_PACKED: return 12;
default:
g_assert_not_reached();
}
}
+static inline int insn_opsize(int insn)
+{
+ switch ((insn >> 6) & 3) {
+ case 0: return OS_BYTE;
+ case 1: return OS_WORD;
+ case 2: return OS_LONG;
+ default: g_assert_not_reached();
+ }
+}
+
/* Assign value to a register. If the width is less than the register width
only the low part of the register is set. */
static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
@@ -1322,19 +1328,7 @@ DISAS_INSN(clr)
{
int opsize;
- switch ((insn >> 6) & 3) {
- case 0: /* clr.b */
- opsize = OS_BYTE;
- break;
- case 1: /* clr.w */
- opsize = OS_WORD;
- break;
- case 2: /* clr.l */
- opsize = OS_LONG;
- break;
- default:
- abort();
- }
+ opsize = insn_opsize(insn);
DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
gen_logic_cc(s, tcg_const_i32(0));
}
@@ -1483,19 +1477,7 @@ DISAS_INSN(tst)
int opsize;
TCGv tmp;
- switch ((insn >> 6) & 3) {
- case 0: /* tst.b */
- opsize = OS_BYTE;
- break;
- case 1: /* tst.w */
- opsize = OS_WORD;
- break;
- case 2: /* tst.l */
- opsize = OS_LONG;
- break;
- default:
- abort();
- }
+ opsize = insn_opsize(insn);
SRC_EA(env, tmp, opsize, 1, NULL);
gen_logic_cc(s, tmp);
}
--
2.5.5
- Re: [Qemu-devel] [PATCH 03/52] target-m68k: define m680x0 CPUs and features, (continued)
- [Qemu-devel] [PATCH 04/52] target-m68k: manage scaled index, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 05/52] target-m68k: introduce read_imXX() functions, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 06/52] target-m68k: set disassembler mode to 680x0 or coldfire, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 07/52] target-m68k: add bkpt instruction, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 08/52] target-m68k: define operand sizes,
Laurent Vivier <=
- [Qemu-devel] [PATCH 09/52] target-m68k: set PAGE_BITS to 12 for m68k, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 10/52] target-m68k: REG() macro cleanup, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 11/52] target-m68k: allow to update flags with operation on words and bytes, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 12/52] target-m68k: Replace helper_xflag_lt with setcond, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 13/52] target-m68k: update CPU flags management, Laurent Vivier, 2016/05/04