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Re: [Qemu-devel] ARM Cortex R5 + VFP3

From: Peter Maydell
Subject: Re: [Qemu-devel] ARM Cortex R5 + VFP3
Date: Tue, 24 May 2016 15:00:52 +0100

On 24 May 2016 at 14:49, Karthik <address@hidden> wrote:
> ahh okay. The code I don't think writes to CPACR_EL1 register, but it runs
> on the hardware anywary.

If it does then there's probably some firmware somewhere
which is doing the setup for you somehow.

As you can see in the Cortex-R5 technical reference manual entry
for CPACR:

the hardware reset value for bits 21..23 is 0, meaning access denied,
and for FPEXC the EN bit is clear on reset:

By the way, QEMU doesn't implement VFPv3-D16, which is what the R5
ought to have -- setting the ARM_FEATURE_VFP3 bit will give you
32 double-precision registers. This is probably close enough that
guest code will work, though obviously if the guest specifically
tests that registers 16..31 don't exist it will not behave as
the hardware does.

-- PMM

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