Re: [Qemu-devel] [PATCH v4 8/9] target-avr: adding instruction translation

[Richard Henderson]

On 06/06/2016 03:37 AM, Michael Rolnik wrote:
> +int avr_translate_AND(CPUAVRState *env, DisasContext *ctx, uint32_t opcode)
> +{
> +    TCGv Rd = cpu_r[AND_Rd(opcode)];
> +    TCGv Rr = cpu_r[AND_Rr(opcode)];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /*  op  */
> +    tcg_gen_and_tl(R, Rd, Rr);             /*  Rd = Rd and Rr  */
> +
> +    /*  Vf  */
> +    tcg_gen_movi_tl(cpu_Vf, 0x00);          /*  Vf = 0  */
> +
> +    /*  Zf  */
> +    tcg_gen_mov_tl(cpu_Zf, R);             /*  Zf = R  */
> +
> +    gen_ZNSf(R);

Double setting of Zf.

> +int avr_translate_BRBC(CPUAVRState *env, DisasContext *ctx, uint32_t opcode)
...
> +int avr_translate_BRBS(CPUAVRState *env, DisasContext *ctx, uint32_t opcode)

You could share some code between these two functions.
See e.g. tcg_invert_cond.

> +    TCGv H = cpu_rampD;
> +
> +    tcg_gen_mov_tl(addr, H);                     /*  addr = H:M:L  */
> +    tcg_gen_shli_tl(addr, addr, 16);

rampD is already shifted.



r~