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Re: [Qemu-devel] [PATCH v3 31/34] linux-user: remove handling of aarch64
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH v3 31/34] linux-user: remove handling of aarch64's EXCP_STREX |
Date: |
Thu, 15 Sep 2016 10:36:57 +0100 |
User-agent: |
mu4e 0.9.17; emacs 25.1.12 |
Richard Henderson <address@hidden> writes:
> From: "Emilio G. Cota" <address@hidden>
>
> The exception is not emitted anymore.
>
> Signed-off-by: Emilio G. Cota <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> Message-Id: <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> linux-user/main.c | 125
> ------------------------------------------------------
> 1 file changed, 125 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 256382a..64838bf 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -868,124 +868,6 @@ void cpu_loop(CPUARMState *env)
>
> #else
>
> -/*
> - * Handle AArch64 store-release exclusive
> - *
> - * rs = gets the status result of store exclusive
> - * rt = is the register that is stored
> - * rt2 = is the second register store (in STP)
> - *
> - */
> -static int do_strex_a64(CPUARMState *env)
> -{
> - uint64_t val;
> - int size;
> - bool is_pair;
> - int rc = 1;
> - int segv = 0;
> - uint64_t addr;
> - int rs, rt, rt2;
> -
> - start_exclusive();
> - /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
> - size = extract32(env->exclusive_info, 0, 2);
> - is_pair = extract32(env->exclusive_info, 2, 1);
> - rs = extract32(env->exclusive_info, 4, 5);
> - rt = extract32(env->exclusive_info, 9, 5);
> - rt2 = extract32(env->exclusive_info, 14, 5);
> -
> - addr = env->exclusive_addr;
> -
> - if (addr != env->exclusive_test) {
> - goto finish;
> - }
> -
> - switch (size) {
> - case 0:
> - segv = get_user_u8(val, addr);
> - break;
> - case 1:
> - segv = get_user_u16(val, addr);
> - break;
> - case 2:
> - segv = get_user_u32(val, addr);
> - break;
> - case 3:
> - segv = get_user_u64(val, addr);
> - break;
> - default:
> - abort();
> - }
> - if (segv) {
> - env->exception.vaddress = addr;
> - goto error;
> - }
> - if (val != env->exclusive_val) {
> - goto finish;
> - }
> - if (is_pair) {
> - if (size == 2) {
> - segv = get_user_u32(val, addr + 4);
> - } else {
> - segv = get_user_u64(val, addr + 8);
> - }
> - if (segv) {
> - env->exception.vaddress = addr + (size == 2 ? 4 : 8);
> - goto error;
> - }
> - if (val != env->exclusive_high) {
> - goto finish;
> - }
> - }
> - /* handle the zero register */
> - val = rt == 31 ? 0 : env->xregs[rt];
> - switch (size) {
> - case 0:
> - segv = put_user_u8(val, addr);
> - break;
> - case 1:
> - segv = put_user_u16(val, addr);
> - break;
> - case 2:
> - segv = put_user_u32(val, addr);
> - break;
> - case 3:
> - segv = put_user_u64(val, addr);
> - break;
> - }
> - if (segv) {
> - goto error;
> - }
> - if (is_pair) {
> - /* handle the zero register */
> - val = rt2 == 31 ? 0 : env->xregs[rt2];
> - if (size == 2) {
> - segv = put_user_u32(val, addr + 4);
> - } else {
> - segv = put_user_u64(val, addr + 8);
> - }
> - if (segv) {
> - env->exception.vaddress = addr + (size == 2 ? 4 : 8);
> - goto error;
> - }
> - }
> - rc = 0;
> -finish:
> - env->pc += 4;
> - /* rs == 31 encodes a write to the ZR, thus throwing away
> - * the status return. This is rather silly but valid.
> - */
> - if (rs < 31) {
> - env->xregs[rs] = rc;
> - }
> -error:
> - /* instruction faulted, PC does not advance */
> - /* either way a strex releases any exclusive lock we have */
> - env->exclusive_addr = -1;
> - end_exclusive();
> - return segv;
> -}
> -
> /* AArch64 main loop */
> void cpu_loop(CPUARMState *env)
> {
> @@ -1026,11 +908,6 @@ void cpu_loop(CPUARMState *env)
> info._sifields._sigfault._addr = env->pc;
> queue_signal(env, info.si_signo, &info);
> break;
> - case EXCP_STREX:
> - if (!do_strex_a64(env)) {
> - break;
> - }
> - /* fall through for segv */
> case EXCP_PREFETCH_ABORT:
> case EXCP_DATA_ABORT:
> info.si_signo = TARGET_SIGSEGV;
> @@ -1066,8 +943,6 @@ void cpu_loop(CPUARMState *env)
> process_pending_signals(env);
> /* Exception return on AArch64 always clears the exclusive monitor,
> * so any return to running guest code implies this.
> - * A strex (successful or otherwise) also clears the monitor, so
> - * we don't need to specialcase EXCP_STREX.
> */
> env->exclusive_addr = -1;
> }
--
Alex Bennée
- [Qemu-devel] [PATCH v3 26/34] target-arm: Rearrange aa32 load and store functions, (continued)
- [Qemu-devel] [PATCH v3 26/34] target-arm: Rearrange aa32 load and store functions, Richard Henderson, 2016/09/03
- [Qemu-devel] [PATCH v3 32/34] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}, Richard Henderson, 2016/09/03
- [Qemu-devel] [PATCH v3 30/34] linux-user: remove handling of ARM's EXCP_STREX, Richard Henderson, 2016/09/03
- [Qemu-devel] [PATCH v3 28/34] target-arm: emulate SWP with atomic_xchg helper, Richard Henderson, 2016/09/03
- [Qemu-devel] [PATCH v3 29/34] target-arm: emulate aarch64's LL/SC using cmpxchg helpers, Richard Henderson, 2016/09/03
- [Qemu-devel] [PATCH v3 31/34] linux-user: remove handling of aarch64's EXCP_STREX, Richard Henderson, 2016/09/03
- Re: [Qemu-devel] [PATCH v3 31/34] linux-user: remove handling of aarch64's EXCP_STREX,
Alex Bennée <=
- [Qemu-devel] [PATCH v3 33/34] target-alpha: Introduce MMU_PHYS_IDX, Richard Henderson, 2016/09/03
- [Qemu-devel] [PATCH v3 34/34] target-alpha: Emulate LL/SC using cmpxchg helpers, Richard Henderson, 2016/09/03
Re: [Qemu-devel] [PATCH v3 00/34] cmpxchg-based emulation of atomics, no-reply, 2016/09/03
Re: [Qemu-devel] [PATCH v3 00/34] cmpxchg-based emulation of atomics, no-reply, 2016/09/03