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[Qemu-devel] [PULL 07/25] aspeed: add support for the AST2500 SoC SMC co
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/25] aspeed: add support for the AST2500 SoC SMC controllers |
Date: |
Mon, 17 Oct 2016 19:40:26 +0100 |
From: Cédric Le Goater <address@hidden>
The SMC controllers on the Aspeed AST2500 SoC are very similar to the
ones found on the AST2400. The differences are on the number of
supported flash modules and their default mappings in the SoC address
space.
The Aspeed AST2500 has one SPI controller for the BMC firmware and two
for the host firmware. All controllers have now the same set of
registers compatible with the AST2400 FMC controller and the legacy
'SMC' controller is fully gone.
We keep the FMC object to act as the BMC SPI controller and add a new
SPI controller for the host. We also have to introduce new type names
to handle the differences in the flash modules memory mappping.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/aspeed_soc.c | 21 +++++++++++++++------
hw/ssi/aspeed_smc.c | 28 +++++++++++++++++++++++++++-
include/hw/arm/aspeed_soc.h | 2 ++
3 files changed, 44 insertions(+), 7 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index b3103f3..e14f5c2 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -25,6 +25,7 @@
#define ASPEED_SOC_IOMEM_BASE 0x1E600000
#define ASPEED_SOC_FMC_BASE 0x1E620000
#define ASPEED_SOC_SPI_BASE 0x1E630000
+#define ASPEED_SOC_SPI2_BASE 0x1E631000
#define ASPEED_SOC_VIC_BASE 0x1E6C0000
#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
#define ASPEED_SOC_SCU_BASE 0x1E6E2000
@@ -38,16 +39,23 @@ static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37,
38, 39, };
#define AST2500_SDRAM_BASE 0x80000000
static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
+static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
-static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE };
+static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
+ ASPEED_SOC_SPI2_BASE};
+static const char *aspeed_soc_ast2500_typenames[] = {
+ "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
static const AspeedSoCInfo aspeed_socs[] = {
{ "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
- 1, aspeed_soc_ast2400_spi_bases },
+ 1, aspeed_soc_ast2400_spi_bases,
+ "aspeed.smc.fmc", aspeed_soc_ast2400_typenames },
{ "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
- 1, aspeed_soc_ast2400_spi_bases },
+ 1, aspeed_soc_ast2400_spi_bases,
+ "aspeed.smc.fmc", aspeed_soc_ast2400_typenames },
{ "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE,
- 1, aspeed_soc_ast2500_spi_bases },
+ 2, aspeed_soc_ast2500_spi_bases,
+ "aspeed.smc.ast2500-fmc", aspeed_soc_ast2500_typenames },
};
/*
@@ -105,12 +113,13 @@ static void aspeed_soc_init(Object *obj)
object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
"hw-strap2", &error_abort);
- object_initialize(&s->fmc, sizeof(s->fmc), "aspeed.smc.fmc");
+ object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
for (i = 0; i < sc->info->spis_num; i++) {
- object_initialize(&s->spi[i], sizeof(s->spi[i]), "aspeed.smc.spi");
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
+ sc->info->spi_typename[i]);
object_property_add_child(obj, "spi", OBJECT(&s->spi[i]), NULL);
qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
}
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 84c1829..21943f4 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -130,6 +130,7 @@
#define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
+#define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
/*
* Default segments mapping addresses and size for each slave per
@@ -142,7 +143,7 @@ static const AspeedSegments aspeed_segments_legacy[] = {
};
static const AspeedSegments aspeed_segments_fmc[] = {
- { 0x20000000, 64 * 1024 * 1024 },
+ { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
{ 0x24000000, 32 * 1024 * 1024 },
{ 0x26000000, 32 * 1024 * 1024 },
{ 0x28000000, 32 * 1024 * 1024 },
@@ -153,6 +154,22 @@ static const AspeedSegments aspeed_segments_spi[] = {
{ 0x30000000, 64 * 1024 * 1024 },
};
+static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
+ { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
+ { 0x28000000, 32 * 1024 * 1024 },
+ { 0x2A000000, 32 * 1024 * 1024 },
+};
+
+static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
+ { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
+ { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
+};
+
+static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
+ { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
+ { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
+};
+
static const AspeedSMCController controllers[] = {
{ "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
CONF_ENABLE_W0, 5, aspeed_segments_legacy,
@@ -163,6 +180,15 @@ static const AspeedSMCController controllers[] = {
{ "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS,
SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi,
ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 },
+ { "aspeed.smc.ast2500-fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
+ CONF_ENABLE_W0, 3, aspeed_segments_ast2500_fmc,
+ ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 },
+ { "aspeed.smc.ast2500-spi1", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
+ CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi1,
+ ASPEED_SOC_SPI_FLASH_BASE, 0x8000000 },
+ { "aspeed.smc.ast2500-spi2", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
+ CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi2,
+ ASPEED_SOC_SPI2_FLASH_BASE, 0x8000000 },
};
static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f26a9f0..5406b49 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -48,6 +48,8 @@ typedef struct AspeedSoCInfo {
hwaddr sdram_base;
int spis_num;
const hwaddr *spi_bases;
+ const char *fmc_typename;
+ const char **spi_typename;
} AspeedSoCInfo;
typedef struct AspeedSoCClass {
--
2.7.4
- [Qemu-devel] [PULL 15/25] tests: add a m25p80 test, (continued)
- [Qemu-devel] [PULL 15/25] tests: add a m25p80 test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 21/25] Fix masking of PC lower bits when doing exception returns, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 19/25] target-arm: Code changes to implement overwrite of tag field on PC load, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 01/25] docs/generic-loader: Update the document, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 17/25] pxa2xx: Auto-assign name for i2c bus in i2c_init_bus., Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 16/25] tests: cleanup ptimer-test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 03/25] target-arm: kvm: use AddressSpace-specific listener, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 09/25] aspeed: add support for the SMC segment registers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 18/25] target-arm: Infrastucture changes to enable handling of tagged address loading into PC, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 07/25] aspeed: add support for the AST2500 SoC SMC controllers,
Peter Maydell <=
- [Qemu-devel] [PULL 23/25] target-arm: Add trace events for the generic timers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 25/25] hw/char/pl011: Add trace events, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 06/25] aspeed: extend the number of host SPI controllers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 22/25] target-arm: Implement dummy MDCCINT_EL1, Peter Maydell, 2016/10/17
- Re: [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/10/18