[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defin
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines |
Date: |
Wed, 11 Jan 2017 21:19:36 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target/sparc/cpu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index b41f5c5..f2e923d 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -336,6 +336,10 @@ enum {
#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
+/* UltraSPARC T1 specific */
+#define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */
+#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */
+
#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
#define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
#define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */
--
1.8.3.1
- [Qemu-devel] [PATCH v2 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2017/01/11
- [Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/11