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Re: [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic
From: |
Stafford Horne |
Subject: |
Re: [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic |
Date: |
Sat, 22 Apr 2017 19:09:42 +0900 |
User-agent: |
Mutt/1.8.0 (2017-02-23) |
On Tue, Apr 18, 2017 at 11:20:55PM +0900, Stafford Horne wrote:
> On Tue, Apr 18, 2017 at 12:52:52AM -0700, Richard Henderson wrote:
> > On 04/16/2017 04:23 PM, Stafford Horne wrote:
> > > In openrisc simulators we use hooks like 'l.nop 1' to cause the
> > > simulator to exit. Implement that for qemu too.
> > >
> > > Reported-by: Waldemar Brodkorb <address@hidden>
> > > Signed-off-by: Stafford Horne <address@hidden>
> >
> > As I said the first time this was posted: This is horrible.
> >
> > If you want to do something like this, it needs to be buried under a special
> > run mode like -semihosting.
>
> Understood, I will revise this. I didnt know this was posted before.
>
> > > case 0x01: /* l.nop */
> > > LOG_DIS("l.nop %d\n", I16);
> > > + {
> > > + TCGv_i32 arg = tcg_const_i32(I16);
> > > + gen_helper_nop(arg);
> > > + }
> >
> > You also really really must special-case l.nop 0 so that it doesn't generate
> > a function call. Just think of all the extra calls you're adding for every
> > delay slot that couldn't be filled.
>
> Yeah, that makes sense. Ill add that for l.nop 0.
FYI,
I am going to drop this patch for now. I think Waldemar can apply this
patch for the time being.
I looked through the semihosting route and I don't think poking l.nop
through there makes much sense since that looks mainly for syscalls. I
also considered making another flag like `-or1k-hacks`, but I figured that
wouldnt be appropriate.
I discussed a bit on #qemu and Alexander Graf suggested to properly define
shutdown semantics for openrisc. Some examples were shown from ppc, s390
and arm.
s390x
http://git.qemu.org/?p=qemu.git;a=blob;f=target/s390x/helper.c;hb=HEAD#l265
Detects the cpu is in WAIT state and shutsdown qemu.
ppc - platform
http://git.qemu.org/?p=qemu.git;a=blob;f=hw/ppc/e500.c;hb=HEAD#l936
Registers hardware device mpc8xxx_gpio which handles shutdown via gpio
I will have a thought about this, it will require some kernel changes.
-Stafford
[Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic, Stafford Horne, 2017/04/16
- Re: [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic, Richard Henderson, 2017/04/18
- Re: [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic, Stafford Horne, 2017/04/18
- Re: [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic,
Stafford Horne <=
- Re: [Qemu-devel] [PATCH 2/7] target/openrisc: add shutdown logic, Richard Henderson, 2017/04/22
- [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR, Stafford Horne, 2017/04/23
- Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR, Richard Henderson, 2017/04/25
- [Qemu-devel] [PATCH RFC v2] target/openrisc: Support non-busy idle state using PMR SPR, Stafford Horne, 2017/04/25
- Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR, Stafford Horne, 2017/04/25
- Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR, Richard Henderson, 2017/04/25
[Qemu-devel] [PATCH 3/7] target/openrisc: add numcores and coreid support, Stafford Horne, 2017/04/16
[Qemu-devel] [PATCH 4/7] target/openrisc: implement shadow registers, Stafford Horne, 2017/04/16