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[Qemu-devel] [PULL 12/27] arm: Don't let no-MPU PMSA cores write to SCTL
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/27] arm: Don't let no-MPU PMSA cores write to SCTLR.M |
Date: |
Thu, 1 Jun 2017 18:10:20 +0100 |
If the CPU is a PMSA config with no MPU implemented, then the
SCTLR.M bit should be RAZ/WI, so that the guest can never
turn on the non-existent MPU.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 404bfdb..f0f25c8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3258,6 +3258,11 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return;
}
+ if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
+ /* M bit is RAZ/WI for PMSA with no MPU implemented */
+ value &= ~SCTLR_M;
+ }
+
raw_write(env, ri, value);
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
--
2.7.4
- [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 12/27] arm: Don't let no-MPU PMSA cores write to SCTLR.M,
Peter Maydell <=
- [Qemu-devel] [PULL 11/27] arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 13/27] arm: Remove unnecessary check on cpu->pmsav7_dregion, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 10/27] arm: Clean up handling of no-MPU PMSA CPUs, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 14/27] armv7m: Improve "-d mmu" tracing for PMSAv7 MPU, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 09/27] arm: Use different ARMMMUIdx values for M profile, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 16/27] arm: All M profile cores are PMSA, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 07/27] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access(), Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 05/27] hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 15/27] armv7m: Implement M profile default memory map, Peter Maydell, 2017/06/01
- [Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU, Peter Maydell, 2017/06/01