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[Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns |
Date: |
Fri, 23 Jun 2017 09:22:34 -0700 |
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/insn-data.def | 9 +++++++++
target/s390x/translate.c | 5 ++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 0555686..8e3f7db 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -134,6 +134,15 @@
D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
D(0xec45, BRXHLE, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 1)
+/* BRANCH PREDICTION PRELOAD */
+ /* ??? Format is SMI, but implemented as NOP, so we need no fields. */
+ C(0xc700, BPP, E, EH, 0, 0, 0, 0, 0, 0)
+/* BRANCH PREDICTION RELATIVE PRELOAD */
+ /* ??? Format is MII, but implemented as NOP, so we need no fields. */
+ C(0xc500, BPRP, E, EH, 0, 0, 0, 0, 0, 0)
+/* NEXT INSTRUCTION ACCESS INTENT */
+ /* ??? Format is IE, but implemented as NOP, so we need no fields. */
+ C(0xb2fa, NIAI, E, EH, 0, 0, 0, 0, 0, 0)
/* CHECKSUM */
C(0xb241, CKSM, RRE, Z, r1_o, ra2, new, r1_32, cksm, 0)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 5275c77..06d5600 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5443,6 +5443,7 @@ enum DisasInsnEnum {
#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /*
load-program-parameter */
#define FAC_DAT_ENH S390_FEAT_DAT_ENH
#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
+#define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
#define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
static const DisasInsn insn_info[] = {
@@ -5556,7 +5557,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env,
DisasContext *s,
case 0x80: /* S */
case 0x82: /* S */
case 0x93: /* S */
- case 0xb2: /* S, RRF, RRE */
+ case 0xb2: /* S, RRF, RRE, IE */
case 0xb3: /* RRE, RRD, RRF */
case 0xb9: /* RRE, RRF */
case 0xe5: /* SSE, SIL */
@@ -5572,6 +5573,8 @@ static const DisasInsn *extract_insn(CPUS390XState *env,
DisasContext *s,
case 0xcc: /* RIL */
op2 = (insn << 12) >> 60;
break;
+ case 0xc5: /* MII */
+ case 0xc7: /* SMI */
case 0xd0 ... 0xdf: /* SS */
case 0xe1: /* SS */
case 0xe2: /* SS */
--
2.9.4
- [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 01/15] target/s390x: Map existing FAC_* names to S390_FEAT_* names, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 02/15] target/s390x: change PSW_SHIFT_KEY, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns,
Richard Henderson <=
- [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction, Richard Henderson, 2017/06/23
- Re: [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Peter Maydell, 2017/06/26