[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte |
Date: |
Fri, 23 Jun 2017 09:22:40 -0700 |
From: David Hildenbrand <address@hidden>
If only the page index is set, most likely we don't have a valid
virtual address. Let's do a full tlb flush for that case.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/mem_helper.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 182c46f..20cef9a 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1630,16 +1630,23 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto,
uint64_t vaddr,
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
if (m4 & 1) {
- tlb_flush_page(cs, page);
- } else {
- tlb_flush_page_all_cpus_synced(cs, page);
- }
-
- /* XXX 31-bit hack */
- if (m4 & 1) {
- tlb_flush_page(cs, page ^ 0x80000000);
+ if (vaddr & ~VADDR_PX) {
+ tlb_flush_page(cs, page);
+ /* XXX 31-bit hack */
+ tlb_flush_page(cs, page ^ 0x80000000);
+ } else {
+ /* looks like we don't have a valid virtual address */
+ tlb_flush(cs);
+ }
} else {
- tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
+ if (vaddr & ~VADDR_PX) {
+ tlb_flush_page_all_cpus_synced(cs, page);
+ /* XXX 31-bit hack */
+ tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
+ } else {
+ /* looks like we don't have a valid virtual address */
+ tlb_flush_all_cpus_synced(cs);
+ }
}
}
--
2.9.4
- [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns, (continued)
- [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte,
Richard Henderson <=
- [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction, Richard Henderson, 2017/06/23
- Re: [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Peter Maydell, 2017/06/26