Re: [Qemu-devel] [sw-dev] RFC: QEMU RISC-V modular ISA decoding

[Michael Clark]

> On 27 Jul 2017, at 8:58 AM, address@hidden wrote:
> 
> 
> Given that one of the goals of RISC-V is extensibility, it would be
> nice if the QEMU port was done in a way to make it easier to extend by
> third parties, including other automated tools.  I'm sure that, over
> time, the preprocessor can be improved to automatically incorporate
> optimizations for better performance.

I had a look at the s390x code in more detail.

It essentially does some length and major opcode unpacking to 
construct/linearise the opcode space, and would be equivalent to constructing a 
15-bit opcode for RISC-V. It does some pre-decoding to find length, majors, and 
has a switch on majors to find instruction type, and then append minors, if any.

- https://hastebin.com/taceyuyore.cpp <https://hastebin.com/taceyuyore.cpp>

It would be akin to something list this (at a high-level):

len = inst_len(inst)            /* bits[1:0] */
op = major_opcode(inst) /* bits[6:2] */

switch op
        - rvc
                /* hairy bit */
        - r-type
                op2 = funct7 << 3 | funct3
        - i-type
        - s-type
                op2 = funct3
        - u-type
                op2 = 0

op = op | op2 << 5