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Re: [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants wi
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values |
Date: |
Tue, 6 Mar 2018 19:56:41 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 03/06/2018 05:43 PM, Michael Clark wrote:
> The RISC-V device-tree code has a number of hard-coded
> constants and this change moves them into header enums.
>
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> hw/riscv/sifive_clint.c | 9 +++------
> hw/riscv/sifive_u.c | 6 ++++--
> hw/riscv/spike.c | 6 ++++--
> hw/riscv/virt.c | 6 ++++--
> include/hw/riscv/sifive_clint.h | 4 ++++
> include/hw/riscv/sifive_u.h | 4 ++++
> include/hw/riscv/spike.h | 4 ++++
> include/hw/riscv/virt.h | 4 ++++
> 8 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
> index 4893453..7cc606e 100644
> --- a/hw/riscv/sifive_clint.c
> +++ b/hw/riscv/sifive_clint.c
> @@ -26,13 +26,10 @@
> #include "hw/riscv/sifive_clint.h"
> #include "qemu/timer.h"
>
> -/* See: riscv-pk/machine/sbi_entry.S and arch/riscv/kernel/time.c */
> -#define TIMER_FREQ (10 * 1000 * 1000)
> -
> static uint64_t cpu_riscv_read_rtc(void)
> {
> - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), TIMER_FREQ,
> - NANOSECONDS_PER_SECOND);
> + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
> + SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
> }
>
> /*
> @@ -59,7 +56,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu,
> uint64_t value)
> diff = cpu->env.timecmp - rtc_r;
> /* back to ns (note args switched in muldiv64) */
> next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> - muldiv64(diff, NANOSECONDS_PER_SECOND, TIMER_FREQ);
> + muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
> timer_mod(cpu->env.timer, next);
> }
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 1c2deef..f3f7615 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -122,7 +122,8 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> g_free(nodename);
>
> qemu_fdt_add_subnode(fdt, "/cpus");
> - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
> + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
> + SIFIVE_CLINT_TIMEBASE_FREQ);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
>
> @@ -131,7 +132,8 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> char *intc =
> g_strdup_printf("/cpus/address@hidden/interrupt-controller", cpu);
> char *isa = riscv_isa_string(&s->soc.harts[cpu]);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
> + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
> + SIFIVE_U_CLOCK_FREQ);
> qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 2d1f114..4c233ec 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -115,7 +115,8 @@ static void create_fdt(SpikeState *s, const struct
> MemmapEntry *memmap,
> g_free(nodename);
>
> qemu_fdt_add_subnode(fdt, "/cpus");
> - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
> + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
> + SIFIVE_CLINT_TIMEBASE_FREQ);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
>
> @@ -124,7 +125,8 @@ static void create_fdt(SpikeState *s, const struct
> MemmapEntry *memmap,
> char *intc =
> g_strdup_printf("/cpus/address@hidden/interrupt-controller", cpu);
> char *isa = riscv_isa_string(&s->soc.harts[cpu]);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
> + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
> + SPIKE_CLOCK_FREQ);
> qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 37968d2..a402856 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -145,7 +145,8 @@ static void create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> g_free(nodename);
>
> qemu_fdt_add_subnode(fdt, "/cpus");
> - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
> + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
> + SIFIVE_CLINT_TIMEBASE_FREQ);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
>
> @@ -155,7 +156,8 @@ static void create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> char *intc =
> g_strdup_printf("/cpus/address@hidden/interrupt-controller", cpu);
> char *isa = riscv_isa_string(&s->soc.harts[cpu]);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
> + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
> + VIRT_CLOCK_FREQ);
> qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
> diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
> index aaa2a58..e2865be 100644
> --- a/include/hw/riscv/sifive_clint.h
> +++ b/include/hw/riscv/sifive_clint.h
> @@ -47,4 +47,8 @@ enum {
> SIFIVE_TIME_BASE = 0xBFF8
> };
>
> +enum {
> + SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
> +};
> +
> #endif
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 662e8a1..be38aa0 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -50,6 +50,10 @@ enum {
> SIFIVE_U_UART1_IRQ = 4
> };
>
> +enum {
> + SIFIVE_U_CLOCK_FREQ = 1000000000
> +};
> +
> #define SIFIVE_U_PLIC_HART_CONFIG "MS"
> #define SIFIVE_U_PLIC_NUM_SOURCES 127
> #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
> diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
> index cb55a14..d85a64e 100644
> --- a/include/hw/riscv/spike.h
> +++ b/include/hw/riscv/spike.h
> @@ -42,6 +42,10 @@ enum {
> SPIKE_DRAM
> };
>
> +enum {
> + SPIKE_CLOCK_FREQ = 1000000000
> +};
> +
> #if defined(TARGET_RISCV32)
> #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
> #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 7525647..2fbe808 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -55,6 +55,10 @@ enum {
> VIRTIO_NDEV = 10
> };
>
> +enum {
> + VIRT_CLOCK_FREQ = 1000000000
> +};
> +
> #define VIRT_PLIC_HART_CONFIG "MS"
> #define VIRT_PLIC_NUM_SOURCES 127
> #define VIRT_PLIC_NUM_PRIORITIES 7
>
- [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 01/22] RISC-V: Make virt create_fdt interface consistent, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/06
- Re: [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 04/22] RISC-V: Use ROM base address and size from memory, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 05/22] RISC-V: Remove redundant identity_translate from, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code and, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure the emulated rom has space for, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in, Michael Clark, 2018/03/06