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[Qemu-devel] [PULL 01/25] target/arm: Add a core count property
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/25] target/arm: Add a core count property |
Date: |
Fri, 9 Mar 2018 17:25:58 +0000 |
From: Alistair Francis <address@hidden>
The cortex A53 TRM specifies that bits 24 and 25 of the L2CTLR register
specify the number of cores in the processor, not the total number of
cores in the system. To report this correctly on machines with multiple
CPU clusters (ARM's big.LITTLE or Xilinx's ZynqMP) we need to allow
the machine to overwrite this value. To do this let's add an optional
property.
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 5 +++++
target/arm/cpu.c | 6 ++++++
target/arm/cpu64.c | 6 ++++--
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8dd6b788df..3fa8fdad21 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -745,6 +745,11 @@ struct ARMCPU {
/* Uniprocessor system with MP extensions */
bool mp_is_up;
+ /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
+ * register.
+ */
+ int32_t core_count;
+
/* The instance init functions for implementation-specific subclasses
* set these fields to specify the implementation-dependent values of
* various constant registers and reset values of non-constant
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6b77aaa445..3e4e9f1873 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -939,6 +939,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cs->num_ases = 1;
}
cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
+
+ /* No core_count specified, default to smp_cpus. */
+ if (cpu->core_count == -1) {
+ cpu->core_count = smp_cpus;
+ }
#endif
qemu_init_vcpu(cs);
@@ -1765,6 +1770,7 @@ static Property arm_cpu_properties[] = {
DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
mp_affinity, ARM64_AFFINITY_INVALID),
DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
+ DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4228713b19..dd9ba973f7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -42,8 +42,10 @@ static inline void unset_feature(CPUARMState *env, int
feature)
#ifndef CONFIG_USER_ONLY
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- /* Number of processors is in [25:24]; otherwise we RAZ */
- return (smp_cpus - 1) << 24;
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ /* Number of cores is in [25:24]; otherwise we RAZ */
+ return (cpu->core_count - 1) << 24;
}
#endif
--
2.16.2
- [Qemu-devel] [PULL 15/25] target/arm: Move definition of 'host' cpu type into cpu.c, (continued)
- [Qemu-devel] [PULL 15/25] target/arm: Move definition of 'host' cpu type into cpu.c, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 09/25] aarch64-linux-user: Add support for EXTRA signal frame records, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 19/25] hw/arm/virt: Support -machine gic-version=max, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 16/25] target/arm: Add "-cpu max" support, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 08/25] aarch64-linux-user: Remove struct target_aux_context, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 06/25] linux-user: Implement aarch64 PR_SVE_SET/GET_VL, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 07/25] aarch64-linux-user: Split out helpers for guest signal handling, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 02/25] hw/arm: Set the core count for Xilinx's ZynqMP, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 22/25] sdcard: Display which protocol is used when tracing (SD or SPI), Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 21/25] sdcard: Display command name when tracing CMD/ACMD, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 01/25] target/arm: Add a core count property,
Peter Maydell <=
- [Qemu-devel] [PULL 14/25] target/arm: Query host CPU features on-demand at instance init, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 05/25] Implement support for i.MX7 Sabre board, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 18/25] hw/arm/virt: Add "max" to the list of CPU types "virt" supports, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 03/25] pci: Add support for Designware IP block, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 17/25] target/arm: Make 'any' CPU just an alias for 'max', Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 20/25] sdcard: Do not trace CMD55, except when we already expect an ACMD, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 24/25] sdhci: Fix a typo in comment, Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 25/25] MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard), Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 04/25] i.MX: Add i.MX7 SOC implementation., Peter Maydell, 2018/03/09
- [Qemu-devel] [PULL 23/25] sdcard: Add the Tuning Command (CMD19), Peter Maydell, 2018/03/09