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[Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree n
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus |
Date: |
Mon, 14 May 2018 17:07:34 -0700 |
To allow Linux to ennumerate devices on the /soc/ node set it as a
"simple-bus".
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3883d7ff9c..f438a72c27 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -97,7 +97,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/soc");
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
- qemu_fdt_setprop_string(fdt, "/soc", "compatible",
"ucbbar,spike-bare-soc");
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
--
2.17.0
- [Qemu-devel] [PATCH v3 0/7] RISC-V: SoCify SiFive boards and connect GEM, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus,
Alistair Francis <=
- [Qemu-devel] [PATCH v3 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/05/14