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[Qemu-devel] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed store instructions |
Date: |
Tue, 3 Jul 2018 15:58:03 +1000 |
From: BALATON Zoltan <address@hidden>
The PPC440 User Manual says that if bit 31 is set, the contents of
CR[CR0] are undefined for indexed store instructions but this form is
not invalid. Other PPC variants confirming to recent ISA where this
bit may be reserved should ignore reserved bits and not raise invalid
instruction exception. In particular, MorphOS has an stwx instruction
with bit 31 set and fails to boot currently because of this. With this
patch it gets further.
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 65c8cc94e7..9eaa10b421 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7054,7 +7054,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
#define GEN_STUX(name, stop, opc2, opc3, type) \
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
-GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
+GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
#define GEN_STS(name, stop, op, type) \
GEN_ST(name, stop, op | 0x20, type) \
GEN_STU(name, stop, op | 0x21, type) \
--
2.17.1
- [Qemu-devel] [PULL 17/35] target/ppc: Split out gen_load_locked, (continued)
- [Qemu-devel] [PULL 17/35] target/ppc: Split out gen_load_locked, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 16/35] target/ppc: Tidy gen_conditional_store, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 12/35] target/ppc: Use atomic load for LQ and LQARX, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 13/35] target/ppc: Use atomic store for STQ, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 25/35] hw/ppc: Give sam46ex its own config option, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 19/35] target/ppc: Split out gen_st_atomic, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 22/35] target/ppc: Implement the rest of gen_ld_atomic, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 23/35] target/ppc: Implement the rest of gen_st_atomic, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed store instructions,
David Gibson <=
- [Qemu-devel] [PULL 33/35] target/ppc: set is_jmp on ppc_tr_breakpoint_check, David Gibson, 2018/07/03
- [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, David Gibson, 2018/07/03
- Re: [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, Mark Cave-Ayland, 2018/07/03
- Re: [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, Sebastian Bauer, 2018/07/03
- Re: [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, Mark Cave-Ayland, 2018/07/04
- Re: [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, Sebastian Bauer, 2018/07/04
- Re: [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, Mark Cave-Ayland, 2018/07/04
- Re: [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, Sebastian Bauer, 2018/07/04
- Re: [Qemu-devel] [Qemu-ppc] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, BALATON Zoltan, 2018/07/04
[Qemu-devel] [PULL 26/35] ppc4xx_i2c: Rewrite to model hardware more closely, David Gibson, 2018/07/03