Re: [Qemu-devel] [PATCH v3 18/40] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions

[Richard Henderson]

On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> +        case NM_ADDIUGP_B:
> +            gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
> +            break;

Use gen_op_addr_add, since behaves_like('DADDIU[GP.B]').

>      case NM_P_LS_U12:
> +    {
> +        uint32_t u = extract32(ctx->opcode, 0, 12);
> +        switch ((ctx->opcode >> 12) & 0x0f) {
> +        case NM_P_PREFU12:
> +            if (rt == 31) {
> +                /* SYNCI */
> +                /* Break the TB to be able to sync copied instructions
> +                   immediately */
> +                ctx->base.is_jmp = DISAS_STOP;

I'll note for future cleanup that while this matches all of the other instances
of SYNCI in target/mips/, this is not actually required.

QEMU supports self-modifying code without any barriers or breaks whatsoever.
(Becuase, of course, i386 as a guest requires this.)


r~