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[Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg |
Date: |
Mon, 23 Jul 2018 15:17:28 -0500 |
From: Richard Henderson <address@hidden>
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
(cherry picked from commit 3d99d931266eaeaf7e83703a53f32232cd6faad7)
Signed-off-by: Michael Roth <address@hidden>
---
target/arm/translate-a64.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c5be901b5f..bcb3b5c5e7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -614,6 +614,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
return v;
}
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
+{
+ TCGv_i32 v = tcg_temp_new_i32();
+
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
+ return v;
+}
+
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
* If SVE is not enabled, then there are only 128 bits in the vector.
*/
@@ -4638,11 +4646,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{
TCGv_ptr fpst = NULL;
- TCGv_i32 tcg_op = tcg_temp_new_i32();
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
TCGv_i32 tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-
switch (opcode) {
case 0x0: /* FMOV */
tcg_gen_mov_i32(tcg_res, tcg_op);
@@ -7538,13 +7544,10 @@ static void
disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_op2);
tcg_temp_free_i64(tcg_res);
} else {
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
TCGv_i64 tcg_res = tcg_temp_new_i64();
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
-
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
@@ -8085,13 +8088,10 @@ static void
disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
fpst = get_fpstatus_ptr(true);
- tcg_op1 = tcg_temp_new_i32();
- tcg_op2 = tcg_temp_new_i32();
+ tcg_op1 = read_fp_hreg(s, rn);
+ tcg_op2 = read_fp_hreg(s, rm);
tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
-
switch (fpopcode) {
case 0x03: /* FMULX */
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
@@ -12010,11 +12010,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
}
if (is_scalar) {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
TCGv_i32 tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-
switch (fpop) {
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
--
2.17.1
- [Qemu-devel] [PATCH 06/99] tcg/arm: Fix memory barrier encoding, (continued)
- [Qemu-devel] [PATCH 06/99] tcg/arm: Fix memory barrier encoding, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 72/99] target/arm: Implement vector shifted FCVT for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 71/99] target/arm: Implement vector shifted SCVF/UCVF for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 73/99] target/arm: Fix float16 to/from int16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 74/99] target/arm: Clear SVE high bits for FMOV, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 76/99] target/arm: Implement FMOV (general) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 77/99] target/arm: Implement FCVT (scalar, integer) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 75/99] fpu/softfloat: Fix conversion from uint64 to float128, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 78/99] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 80/99] target/arm: Implement FP data-processing (2 source) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg,
Michael Roth <=
- [Qemu-devel] [PATCH 07/99] target/arm: Implement v8M VLLDM and VLSTM, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 81/99] target/arm: Implement FP data-processing (3 source) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 84/99] target/arm: Implement FMOV (immediate) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 83/99] target/arm: Implement FCSEL for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 82/99] target/arm: Implement FCMP for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 85/99] target/arm: Fix sqrt_f16 exception raising, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 86/99] hw/isa/superio: Fix inconsistent use of Chardev->be, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 87/99] mux: fix ctrl-a b again, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 88/99] nfs: Remove processed options from QDict, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 89/99] replace functions which are only available in glib-2.24, Michael Roth, 2018/07/23