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Re: [Qemu-devel] [PATCH v6 40/77] target/mips: Add emulation of DSP ASE
From: |
Aleksandar Markovic |
Subject: |
Re: [Qemu-devel] [PATCH v6 40/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3 |
Date: |
Fri, 3 Aug 2018 11:27:41 +0000 |
> From: Stefan Markovic <address@hidden>
> Sent: Thursday, August 2, 2018 4:16 PM
> Subject: [PATCH v6 40/77] target/mips: Add emulation of DSP ASE for nanoMIPS
> - part 3
>
> From: Stefan Markovic <address@hidden>
>
> Add emulation of DSP ASE instructions for nanoMIPS - part 3.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
> target/mips/translate.c | 186
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 186 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 06707ac..3f41728 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -16869,13 +16869,197 @@ static void
> gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
> }
> }
>
> + case NM_POOL32AXF_1_0:
> + switch (extract32(ctx->opcode, 12, 2)) {
> + case NM_MFHI:
> + gen_HILO(ctx, OPC_MFHI, v2 >> 3, ret);
> + break;
> + case NM_MFLO:
> + gen_HILO(ctx, OPC_MFLO, v2 >> 3, ret);
> + break;
> + case NM_MTHI:
> + gen_HILO(ctx, OPC_MTHI, v2 >> 3, v1);
> + break;
> + case NM_MTLO:
> + gen_HILO(ctx, OPC_MTLO, v2 >> 3, v1);
> + break;
> + }
> + break;
Missing availability control (check_dsp() or similar), here and in many other
places in this patch.
> + case NM_POOL32AXF_1_1:
> + switch (extract32(ctx->opcode, 12, 2)) {
> + case NM_MTHLIP:
> + tcg_gen_movi_tl(t0, v2);
> + gen_helper_mthlip(t0, v0_t, cpu_env);
> + break;
> + case NM_SHILOV:
> + tcg_gen_movi_tl(t0, v2 >> 3);
> + gen_helper_shilo(t0, v0_t, cpu_env);
> + break;
> + }
> + break;
Missing default case, availability control.
> + case NM_POOL32AXF_1_3:
> + imm = extract32(ctx->opcode, 14, 7);
> + switch (extract32(ctx->opcode, 12, 2)) {
> + case NM_RDDSP:
> + tcg_gen_movi_tl(t0, imm);
> + gen_helper_rddsp(t0, t0, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + case NM_WRDSP:
> + gen_load_gpr(t0, ret);
> + tcg_gen_movi_tl(t1, imm);
> + gen_helper_wrdsp(t0, t1, cpu_env);
> + break;
> + case NM_EXTP:
> + tcg_gen_movi_tl(t0, v2 >> 3);
> + tcg_gen_movi_tl(t1, v1);
> + gen_helper_extp(t0, t0, t1, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + case NM_EXTPDP:
> + tcg_gen_movi_tl(t0, v2 >> 3);
> + tcg_gen_movi_tl(t1, v1);
> + gen_helper_extpdp(t0, t0, t1, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + }
> + break;
Missing availability control.
> + case NM_POOL32AXF_1_5:
> + {
> + opc = extract32(ctx->opcode, 12, 2);
> + gen_pool32axf_1_5_nanomips_insn(ctx, opc, ret, v1, v2);
> + }
> + break;
Missing availability control, spurious indentation.
> + case NM_POOL32AXF_1_7:
> + tcg_gen_movi_tl(t0, v2 >> 3);
> + tcg_gen_movi_tl(t1, v1);
> + switch (extract32(ctx->opcode, 12, 2)) {
> + case NM_EXTR_W:
> + gen_helper_extr_w(t0, t0, t1, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + case NM_EXTR_R_W:
> + gen_helper_extr_r_w(t0, t0, t1, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + case NM_EXTR_RS_W:
> + gen_helper_extr_rs_w(t0, t0, t1, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + case NM_EXTR_S_H:
> + gen_helper_extr_s_h(t0, t0, t1, cpu_env);
> + gen_store_gpr(t0, ret);
> + break;
> + }
> + break;
Missing availability control.
Aleksandar M.
- [Qemu-devel] [PATCH v6 34/77] target/mips: Implement emulation of nanoMIPS EXTW instruction, (continued)
- [Qemu-devel] [PATCH v6 34/77] target/mips: Implement emulation of nanoMIPS EXTW instruction, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 35/77] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 36/77] target/mips: Add emulation of nanoMIPS 32-bit branch instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 37/77] target/mips: Implement MT ASE support for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 38/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 39/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 40/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Stefan Markovic, 2018/08/02
- Re: [Qemu-devel] [PATCH v6 40/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v6 41/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 42/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 43/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 44/77] target/mips: Add handling of branch delay slots for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 45/77] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 46/77] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 47/77] target/mips: Implement CP0 Config1.WR bit functionality, Stefan Markovic, 2018/08/02