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[Qemu-devel] [PULL 3/8] i386: Add CPUID bit and feature words for IA32_A
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 3/8] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR |
Date: |
Thu, 16 Aug 2018 22:33:55 -0300 |
From: Robert Hoo <address@hidden>
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.
Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b5c6686fe2..878444755f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -690,6 +690,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network
Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation
Single Precision */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
+#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass
Disable */
#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction
Barrier */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 723e02221e..2bf9fcc556 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1000,12 +1000,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]
= {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, "spec-ctrl", NULL,
- NULL, NULL, NULL, "ssbd",
+ NULL, "arch-capabilities", NULL, "ssbd",
},
.cpuid_eax = 7,
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
.cpuid_reg = R_EDX,
.tcg_features = TCG_7_0_EDX_FEATURES,
+ .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
},
[FEAT_8000_0007_EDX] = {
.feat_names = {
--
2.18.0.rc1.1.g3f1ff2140
- [Qemu-devel] [PULL 0/8] x86 queue, 2018-08-16, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 2/8] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 3/8] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR,
Eduardo Habkost <=
- [Qemu-devel] [PULL 1/8] docs: add guidance on configuring CPU models for x86, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 4/8] i386: Add CPUID bit for PCONFIG, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 5/8] i386: Add CPUID bit for WBNOINVD, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 7/8] target-i386: adds PV_SEND_IPI CPUID feature bit, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 6/8] i386: Add new CPU model Icelake-{Server, Client}, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 8/8] i386: Disable TOPOEXT by default on "-cpu host", Eduardo Habkost, 2018/08/16
- Re: [Qemu-devel] [PULL 0/8] x86 queue, 2018-08-16, Peter Maydell, 2018/08/17
- Re: [Qemu-devel] [PULL 0/8] x86 queue, 2018-08-16, no-reply, 2018/08/17