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[Qemu-devel] [PULL v2 07/10] target/riscv: call gen_goto_tb on DISAS_TOO
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PULL v2 07/10] target/riscv: call gen_goto_tb on DISAS_TOO_MANY |
Date: |
Wed, 5 Sep 2018 15:09:30 -0700 |
From: "Emilio G. Cota" <address@hidden>
Performance impact of this and the previous commits, measured with
the very-easy-to-cross-compile rv8-bench:
https://github.com/rv8-io/rv8-bench
Host: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz
- Key:
before: master
after1,2,3: the 3 commits in this series (i.e. 3 is this commit)
- User-mode:
bench before after1 after2 after3 final speedup
---------------------------------------------------------
aes 1.12s 1.12s 1.10s 1.00s 1.12
bigint 0.78s 0.78s 0.78s 0.78s 1
dhrystone 0.96s 0.97s 0.49s 0.49s 1.9591837
miniz 1.94s 1.94s 1.88s 1.86s 1.0430108
norx 0.51s 0.51s 0.49s 0.48s 1.0625
primes 0.85s 0.85s 0.84s 0.84s 1.0119048
qsort 4.87s 4.88s 1.86s 1.86s 2.6182796
sha512 0.76s 0.77s 0.64s 0.64s 1.1875
(after1 only applies to softmmu, so no surprises here)
- Full-system (fedora):
bench before after1 after2 after3 final speedup
---------------------------------------------------------
aes 2.68s 2.54s 2.60s 2.34s 1.1452991
bigint 1.61s 1.56s 1.55s 1.64s 0.98170732
dhrystone 1.78s 1.67s 1.25s 1.24s 1.4354839
miniz 3.53s 3.35s 3.28s 3.35s 1.0537313
norx 1.13s 1.09s 1.07s 1.06s 1.0660377
primes 15.37s 15.41s 15.20s 15.37s 1
qsort 7.20s 6.71s 3.85s 3.96s 1.8181818
sha512 1.07s 1.04s 0.90s 0.90s 1.1888889
SoftMMU slows things down, so the numbers are less sensitive.
Cross-page jumps improve things a little bit, though.
Note that I'm not showing here averages, just results from a
single run, so with primes there isn't much to worry about.
Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 66a80ca772..18d7b6d147 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1868,12 +1868,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_exit_tb(NULL, 0);
- }
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NORETURN:
break;
--
2.17.1
- [Qemu-devel] [PULL v2 00/10] riscv-pullreq queue, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 01/10] RISC-V: Update address bits to support sv39 and sv48, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 02/10] RISC-V: Improve page table walker spec compliance, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 03/10] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 09/10] hw/riscv/spike: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 05/10] target/riscv: optimize cross-page direct jumps in softmmu, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 04/10] RISC-V: Simplify riscv_cpu_local_irqs_pending, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 07/10] target/riscv: call gen_goto_tb on DISAS_TOO_MANY,
Alistair Francis <=
- [Qemu-devel] [PULL v2 06/10] target/riscv: optimize indirect branches, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 08/10] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/09/05
- Re: [Qemu-devel] [PULL v2 00/10] riscv-pullreq queue, Peter Maydell, 2018/09/24