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Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific thre
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU |
Date: |
Wed, 26 Sep 2018 23:43:46 +0100 (BST) |
User-agent: |
Alpine 2.21 (LFD 202 2017-01-01) |
On Thu, 27 Sep 2018, Philippe Mathieu-Daudé wrote:
> > +static void gen_mul_r5900(DisasContext *ctx, uint32_t opc,
> > + int acc, int rd, int rs, int rt)
>
> Since we have acc = 0 we can directly use cpu_LO[0] and cpu_HI[0],
> removing needs for an 'acc' argument.
Corresponding MULT1 and MULTU1 instructions use `acc = 1' though, as do
similar variations of all the other MDU instructions. Maybe the addition
of the required `acc' argument could be staged for a separate patch with
all the pipeline 1 MDU instructions though.
Maciej
- [Qemu-devel] [PATCH v5 0/8] target/mips: Support R5900 GCC programs in user mode, Fredrik Noring, 2018/09/19
- [Qemu-devel] [PATCH v5 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/19
- [Qemu-devel] [PATCH v5 4/8] target/mips: Add function to signal RI exception unless user only, Fredrik Noring, 2018/09/19
- [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/19
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/26
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU,
Maciej W. Rozycki <=
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Maciej W. Rozycki, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/28
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Maciej W. Rozycki, 2018/09/28
[Qemu-devel] [PATCH v5 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/19
[Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/19