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Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific thre
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU |
Date: |
Sun, 30 Sep 2018 23:20:26 +0100 (BST) |
User-agent: |
Alpine 2.21 (LFD 202 2017-01-01) |
On Sun, 30 Sep 2018, Philippe Mathieu-Daudé wrote:
> > TX79 do not implement DMULT or DMULTU, the Tx49 does and they do support
> > the extra `rd' operand there[1]. Still no DMADD or DMADDU though.
>
> As does the TX39.
Umm, the TX39 is 32-bit and does not have 64-bit instructions, so it
can't have DMULT or DMULTU.
> There is also the TX99 series (based on 25Kf):
> https://www.toshiba.co.jp/about/press/2002_02/pr1901.htm
Hmm, did the TX99 actually tape out? I thought the 25Kf was withdrawn
and never made it to market. I only saw a couple of 25Kf LVs on Malta CPU
daughtercards back in my MIPS UK days in mid 2000s.
Maciej
- [Qemu-devel] [PATCH v6 0/7] target/mips: Limited support for the R5900, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 1/7] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/29
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/30
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Maciej W. Rozycki, 2018/09/30
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/30
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Maciej W. Rozycki, 2018/09/30
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/30
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU,
Maciej W. Rozycki <=
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/30
- Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Philippe Mathieu-Daudé, 2018/09/30
[Qemu-devel] [PATCH v6 5/7] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/29
[Qemu-devel] [PATCH v6 4/7] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/09/29
[Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/29
[Qemu-devel] [PATCH v6 7/7] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/29