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[Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interr
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts |
Date: |
Thu, 4 Oct 2018 20:06:18 +0000 |
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis <address@hidden>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
- VIRTIO_NDEV = 10
+ VIRTIO_NDEV = 0x35
};
enum {
--
2.17.1
- [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts,
Alistair Francis <=
- [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 3/5] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/10/04
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Andrea Bolognani, 2018/10/10