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Re: [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe |
Date: |
Thu, 25 Oct 2018 19:47:04 +0100 |
On 4 October 2018 at 21:06, Alistair Francis <address@hidden> wrote:
> Connect the gpex PCIe device based on the device tree included in the
> HiFive Unleashed ROM.
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> default-configs/riscv32-softmmu.mak | 6 ++-
> default-configs/riscv64-softmmu.mak | 6 ++-
> hw/riscv/virt.c | 58 +++++++++++++++++++++++++++++
> include/hw/riscv/virt.h | 4 +-
> 4 files changed, 71 insertions(+), 3 deletions(-)
> +static inline DeviceState *
> +gpex_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
> + hwaddr cfg_base, uint64_t cfg_size,
> + hwaddr mmio_base, uint64_t mmio_size,
> + qemu_irq irq, bool link_up)
> +{
> + DeviceState *dev;
> + MemoryRegion *cfg, *mmio;
> +
> + dev = qdev_create(NULL, TYPE_GPEX_HOST);
> +
> + qdev_init_nofail(dev);
> +
> + cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> + memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
> +
> + mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
> + memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
You probably also want to map the gpex's mmio region 2,
which is the PCI IO BAR window. Otherwise PCI devices
with IO BARs won't work right.
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
GPEX has 4 interrupt lines, corresponding to classic PCI
IRQs A, B, C, D. You need to wire them all up, or only the
first PCI device plugged in will have a working interrupt.
You also don't look to have the bit of device-tree generation
that sets up the interrupt-map, which tells the guest about
the mapping from PCI devfns (ie, which slot the card is in) to
IRQ lines.
> +
> + return dev;
> +}
> +
> static void riscv_virt_board_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = virt_memmap;
> @@ -382,6 +436,10 @@ static void riscv_virt_board_init(MachineState *machine)
> qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
> }
>
> + gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
> + memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
You could put the MMIO BAR window base and size in your memmap[] too...
> + qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ),
> true);
thanks
-- PMM
- [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/10/04
- Re: [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 3/5] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/10/04
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Andrea Bolognani, 2018/10/10