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[Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0 |
Date: |
Tue, 16 Oct 2018 16:23:11 +0100 |
From: Richard Henderson <address@hidden>
The incorrect value advertised only thumb2 div without arm div.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7ea7e4c1316..cd48ad42d87 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1587,7 +1587,10 @@ static void cortex_a7_initfn(Object *obj)
cpu->id_mmfr1 = 0x40000000;
cpu->id_mmfr2 = 0x01240000;
cpu->id_mmfr3 = 0x02102211;
- cpu->id_isar0 = 0x01101110;
+ /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+ * table 4-41 gives 0x02101110, which includes the arm div insns.
+ */
+ cpu->id_isar0 = 0x02101110;
cpu->id_isar1 = 0x13112111;
cpu->id_isar2 = 0x21232041;
cpu->id_isar3 = 0x11112131;
--
2.19.0
- [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 07/19] net: cadence_gem: Announce availability of priority queues, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 04/19] target/arm: Align cortex-r5 id_isar0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 06/19] net: cadence_gem: Disable TSU feature bit, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0,
Peter Maydell <=
- [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of descriptor words, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters, Peter Maydell, 2018/10/16