[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on suppor
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters |
Date: |
Tue, 16 Oct 2018 16:23:23 +0100 |
From: Aaron Lindsay <address@hidden>
This is an amendment to my earlier patch:
commit 7ece99b17e832065236c07a158dfac62619ef99b
Author: Aaron Lindsay <address@hidden>
Date: Thu Apr 26 11:04:39 2018 +0100
target/arm: Mask PMU register writes based on PMCR_EL0.N
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 138a1f15405..7a53098888d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1179,6 +1179,7 @@ static void pmcntenclr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ value &= pmu_counter_mask(env);
env->cp15.c9_pmovsr &= ~value;
}
--
2.19.0
- [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0, (continued)
- [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of descriptor words, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters,
Peter Maydell <=
- [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72, Peter Maydell, 2018/10/16