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[Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SE
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> |
Date: |
Wed, 17 Oct 2018 14:33:53 +0200 |
From: Matthew Fortune <address@hidden>
Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions.
Their handling was permuted.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Matthew Fortune <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index aceda11..7f97f08 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -15642,15 +15642,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case 0x38:
/* cmovs */
switch ((ctx->opcode >> 6) & 0x7) {
- case MOVN_FMT: /* SELNEZ_FMT */
+ case MOVN_FMT: /* SELEQZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
- /* SELNEZ_FMT */
+ /* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
- gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
- gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
@@ -15664,15 +15664,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVN);
break;
- case MOVZ_FMT: /* SELEQZ_FMT */
+ case MOVZ_FMT: /* SELNEZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
- /* SELEQZ_FMT */
+ /* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
- gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
- gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
--
2.7.4
- [Qemu-devel] [PULL 04/27] elf: Add Mips_elf_abiflags_v0 structure, (continued)
- [Qemu-devel] [PULL 04/27] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 10/27] target/mips: Add assembler mnemonics list for MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 01/27] mailmap: Add an item for Yongbok Kim, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 07/27] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 16/27] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/17