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[Qemu-devel] [PULL v2 27/28] target/mips: Fix misplaced 'break' in handl
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 27/28] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH |
Date: |
Thu, 18 Oct 2018 20:47:52 +0200 |
From: Stefan Markovic <address@hidden>
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by
Coverity (CID 1395627).
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2890219..12f2aec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19970,8 +19970,8 @@ static void gen_pool32a5_nanomips_insn(DisasContext
*ctx, int opc,
case 0:
/* SHRA_PH */
gen_helper_shra_ph(v1_t, t0, v1_t);
- break;
gen_store_gpr(v1_t, rt);
+ break;
case 1:
/* SHRA_R_PH */
gen_helper_shra_r_ph(v1_t, t0, v1_t);
--
2.7.4
- [Qemu-devel] [PULL v2 13/28] target/mips: Add opcode values of MXU ASE, (continued)
- [Qemu-devel] [PULL v2 13/28] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 08/28] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 20/28] target/mips: Add CP0 PWBase register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 15/28] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 17/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 07/28] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 22/28] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 21/28] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 19/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 24/28] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 27/28] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 14/28] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 10/28] target/mips: Add basic description of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 12/28] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 23/28] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 18/28] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 28/28] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 26/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 25/28] target/mips: Implement hardware page table walker for MIPS32, Aleksandar Markovic, 2018/10/18
- Re: [Qemu-devel] [PULL v2 00/28] MIPS queue October 2018, part 1, v2, Peter Maydell, 2018/10/19