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[Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL |
Date: |
Fri, 19 Oct 2018 17:57:23 +0100 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 70 +++++++++++++++++++++++++++++-------------
1 file changed, 48 insertions(+), 22 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7b13717c0dc..2d715d9b47b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6373,8 +6373,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
size--;
}
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
- /* To avoid excessive duplication of ops we implement shift
- by immediate using the variable shift operations. */
if (op < 8) {
/* Shift by immediate:
VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
@@ -6386,37 +6384,62 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
}
/* Right shifts are encoded as N - shift, where N is the
element size in bits. */
- if (op <= 4)
+ if (op <= 4) {
shift = shift - (1 << (size + 3));
+ }
+
+ switch (op) {
+ case 0: /* VSHR */
+ /* Right shift comes here negative. */
+ shift = -shift;
+ /* Shifts larger than the element size are architecturally
+ * valid. Unsigned results in all zeros; signed results
+ * in all sign bits.
+ */
+ if (!u) {
+ tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
+ MIN(shift, (8 << size) - 1),
+ vec_size, vec_size);
+ } else if (shift >= 8 << size) {
+ tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
+ } else {
+ tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
+ vec_size, vec_size);
+ }
+ return 0;
+
+ case 5: /* VSHL, VSLI */
+ if (!u) { /* VSHL */
+ /* Shifts larger than the element size are
+ * architecturally valid and results in zero.
+ */
+ if (shift >= 8 << size) {
+ tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
+ } else {
+ tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
+ vec_size, vec_size);
+ }
+ return 0;
+ }
+ break;
+ }
+
if (size == 3) {
count = q + 1;
} else {
count = q ? 4: 2;
}
- switch (size) {
- case 0:
- imm = (uint8_t) shift;
- imm |= imm << 8;
- imm |= imm << 16;
- break;
- case 1:
- imm = (uint16_t) shift;
- imm |= imm << 16;
- break;
- case 2:
- case 3:
- imm = shift;
- break;
- default:
- abort();
- }
+
+ /* To avoid excessive duplication of ops we implement shift
+ * by immediate using the variable shift operations.
+ */
+ imm = dup_const(size, shift);
for (pass = 0; pass < count; pass++) {
if (size == 3) {
neon_load_reg64(cpu_V0, rm + pass);
tcg_gen_movi_i64(cpu_V1, imm);
switch (op) {
- case 0: /* VSHR */
case 1: /* VSRA */
if (u)
gen_helper_neon_shl_u64(cpu_V0, cpu_V0,
cpu_V1);
@@ -6447,6 +6470,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
cpu_V0, cpu_V1);
}
break;
+ default:
+ g_assert_not_reached();
}
if (op == 1 || op == 3) {
/* Accumulate. */
@@ -6475,7 +6500,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
tmp2 = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp2, imm);
switch (op) {
- case 0: /* VSHR */
case 1: /* VSRA */
GEN_NEON_INTEGER_OP(shl);
break;
@@ -6513,6 +6537,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case 7: /* VQSHL */
GEN_NEON_INTEGER_OP_ENV(qshl);
break;
+ default:
+ g_assert_not_reached();
}
tcg_temp_free_i32(tmp2);
--
2.19.1
- [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes, (continued)
- [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 41/45] target/arm: Reorg NEON VLD/VST single element to one lane, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 40/45] target/arm: Promote consecutive memory ops for aa32, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 39/45] target/arm: Reorg NEON VLD/VST all elements, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 37/45] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 34/45] target/arm: Use gvec for VSRA, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL,
Peter Maydell <=
- [Qemu-devel] [PULL 32/45] target/arm: Use gvec for NEON_3R_VMUL, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 31/45] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 30/45] target/arm: Use gvec for NEON_3R_VADD_VSUB insns, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 29/45] target/arm: Use gvec for NEON_3R_LOGIC insns, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 27/45] target/arm: Use gvec for NEON VDUP, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 28/45] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate), Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 26/45] target/arm: Mark some arrays const, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 25/45] target/arm: Promote consecutive memory ops for aa64, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 24/45] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count, Peter Maydell, 2018/10/19