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[Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count |
Date: |
Fri, 19 Oct 2018 17:57:13 +0100 |
From: Richard Henderson <address@hidden>
This is done generically in translator_loop.
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 1 -
target/arm/translate.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 371909620bb..c3a0e5accd8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -13899,7 +13899,6 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
{
- tcg_clear_temp_count();
}
static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1bf339a98b6..7d7a48e5b93 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12701,7 +12701,6 @@ static void arm_tr_tb_start(DisasContextBase *dcbase,
CPUState *cpu)
tcg_gen_movi_i32(tmp, 0);
store_cpu_field(tmp, condexec_bits);
}
- tcg_clear_temp_count();
}
static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
--
2.19.1
- [Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL, (continued)
- [Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 32/45] target/arm: Use gvec for NEON_3R_VMUL, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 31/45] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 30/45] target/arm: Use gvec for NEON_3R_VADD_VSUB insns, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 29/45] target/arm: Use gvec for NEON_3R_LOGIC insns, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 27/45] target/arm: Use gvec for NEON VDUP, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 28/45] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate), Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 26/45] target/arm: Mark some arrays const, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 25/45] target/arm: Promote consecutive memory ops for aa64, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 24/45] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count,
Peter Maydell <=
- [Qemu-devel] [PULL 19/45] target/arm: Get IL bit correct for v7 syndrome values, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 18/45] target/arm: New utility function to extract EC from syndrome, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 17/45] target/arm: Implement HCR.PTW, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 16/45] target/arm: Implement HCR.VI and VF, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 15/45] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 14/45] target/arm: Implement HCR.DC, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 12/45] target/arm: Make switch_mode() file-local, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 13/45] target/arm: Implement HCR.FB, Peter Maydell, 2018/10/19