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[Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2 |
Date: |
Mon, 22 Oct 2018 14:57:23 +0200 |
From: Aleksandar Markovic <address@hidden>
The following changes since commit b312532fd03413d0e6ae6767ec793a3e30f487b8:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2018-10-19 19:01:07 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-oct-2018-part-2
for you to fetch changes up to 2ec219776c633df9e43c5fa1557f70ee4f735f9d:
target/mips: Fix decoding of ALIGN and DALIGN instructions (2018-10-22
14:41:47 +0200)
----------------------------------------------------------------
MIPS queue for October 2018 - part 2
Limited support for R5900 ISA, MMI ASE, and two misc fixes.
----------------------------------------------------------------
Aleksandar Markovic (2):
target/mips: Fix the title of translate.c
target/mips: Fix decoding of ALIGN and DALIGN instructions
Fredrik Noring (32):
target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor
constants
disas/mips: Define R5900 disassembly constants
target/mips: R5900 Multimedia Instruction overview note
target/mips: Define R5900 MMI class, and LQ and SQ opcode constants
target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode
constants
target/mips: Define R5900 MMI0 opcode constants
target/mips: Define R5900 MMI1 opcode constants
target/mips: Define R5900 MMI2 opcode constants
target/mips: Define R5900 MMI3 opcode constants
target/mips: Placeholder for R5900 SQ, handle user mode RDHWR
target/mips: Placeholder for R5900 LQ
target/mips: Placeholder for R5900 MMI instruction class
target/mips: Placeholder for R5900 MMI0 instruction subclass
target/mips: Placeholder for R5900 MMI1 instruction subclass
target/mips: Placeholder for R5900 MMI2 instruction subclass
target/mips: Placeholder for R5900 MMI3 instruction subclass
target/mips: Support R5900 three-operand MULT and MULTU instructions
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
target/mips: Support R5900 DIV1 and DIVU1 instructions
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS
IV
target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only
tests/tcg/mips: Test R5900 three-operand MULT
tests/tcg/mips: Test R5900 three-operand MULTU
tests/tcg/mips: Test R5900 three-operand MULT1
tests/tcg/mips: Test R5900 three-operand MULTU1
tests/tcg/mips: Test R5900 MFLO1 and MFHI1
tests/tcg/mips: Test R5900 MTLO1 and MTHI1
tests/tcg/mips: Test R5900 DIV1
tests/tcg/mips: Test R5900 DIVU1
target/mips: Define the R5900 CPU
linux-user/mips: Recognise the R5900 CPU model
disas/mips.c | 16 +
linux-user/mips/target_elf.h | 3 +
target/mips/mips-defs.h | 3 +
target/mips/translate.c | 865 ++++++++++++++++++++++++++++++++++++-
target/mips/translate_init.inc.c | 59 +++
tests/tcg/mips/mipsr5900/Makefile | 30 ++
tests/tcg/mips/mipsr5900/div1.c | 73 ++++
tests/tcg/mips/mipsr5900/divu1.c | 48 ++
tests/tcg/mips/mipsr5900/mflohi1.c | 35 ++
tests/tcg/mips/mipsr5900/mtlohi1.c | 40 ++
tests/tcg/mips/mipsr5900/mult.c | 76 ++++
tests/tcg/mips/mipsr5900/multu.c | 68 +++
12 files changed, 1297 insertions(+), 19 deletions(-)
create mode 100644 tests/tcg/mips/mipsr5900/Makefile
create mode 100644 tests/tcg/mips/mipsr5900/div1.c
create mode 100644 tests/tcg/mips/mipsr5900/divu1.c
create mode 100644 tests/tcg/mips/mipsr5900/mflohi1.c
create mode 100644 tests/tcg/mips/mipsr5900/mtlohi1.c
create mode 100644 tests/tcg/mips/mipsr5900/mult.c
create mode 100644 tests/tcg/mips/mipsr5900/multu.c
--
2.7.4
- [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 02/34] disas/mips: Define R5900 disassembly constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 08/34] target/mips: Define R5900 MMI2 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 09/34] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 07/34] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 03/34] target/mips: R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/22