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[Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 opcode constant
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 opcode constants |
Date: |
Mon, 22 Oct 2018 14:57:29 +0200 |
From: Fredrik Noring <address@hidden>
Add definition of MI0 opcodes.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ae98817..242f2df 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2180,6 +2180,57 @@ enum {
TX79_MMI_PSRAW = 0x3F | TX79_CLASS_MMI,
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI0:
+ *
+ * 31 26 10 6 5 0
+ * +--------+----------------------+--------+--------+
+ * | MMI | |function| MMI0 |
+ * +--------+----------------------+--------+--------+
+ *
+ * function bits 7..6
+ * bits | 0 | 1 | 2 | 3
+ * 10..8 | 00 | 01 | 10 | 11
+ * -------+-------+-------+-------+-------
+ * 0 000 | PADDW | PSUBW | PCGTW | PMAXW
+ * 1 001 | PADDH | PSUBH | PCGTH | PMAXH
+ * 2 010 | PADDB | PSUBB | PCGTB | *
+ * 3 011 | * | * | * | *
+ * 4 100 | PADDSW| PSUBSW| PEXTLW| PPACW
+ * 5 101 | PADDSH| PSUBSH| PEXTLH| PPACH
+ * 6 110 | PADDSB| PSUBSB| PEXTLB| PPACB
+ * 7 111 | * | * | PEXT5 | PPAC5
+ */
+
+#define MASK_TX79_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
+enum {
+ TX79_MMI0_PADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBW = (0x01 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PCGTW = (0x02 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PMAXW = (0x03 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDH = (0x04 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBH = (0x05 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PCGTH = (0x06 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PMAXH = (0x07 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDB = (0x08 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBB = (0x09 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PCGTB = (0x0A << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDSW = (0x10 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBSW = (0x11 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXTLW = (0x12 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPACW = (0x13 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDSH = (0x14 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBSH = (0x15 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXTLH = (0x16 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPACH = (0x17 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDSB = (0x18 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBSB = (0x19 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXTLB = (0x1A << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPACB = (0x1B << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXT5 = (0x1E << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPAC5 = (0x1F << 6) | TX79_MMI_CLASS_MMI0,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.7.4
- [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 02/34] disas/mips: Define R5900 disassembly constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 08/34] target/mips: Define R5900 MMI2 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 09/34] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 07/34] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 opcode constants,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 03/34] target/mips: R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/22