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[Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR |
Date: |
Mon, 22 Oct 2018 14:57:33 +0200 |
From: Fredrik Noring <address@hidden>
Add placeholder for SQ instruction, handle RDHWR.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3c6a2c9..19a8aba 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,53 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
}
}
+static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
+{
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */
+}
+
+/*
+ * The TX79-specific instruction Store Quadword
+ *
+ * +--------+-------+-------+------------------------+
+ * | 011111 | base | rt | offset | SQ
+ * +--------+-------+-------+------------------------+
+ * 6 5 5 16
+ *
+ * has the same opcode as the Read Hardware Register instruction
+ *
+ * +--------+-------+-------+-------+-------+--------+
+ * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
+ * +--------+-------+-------+-------+-------+--------+
+ * 6 5 5 5 5 6
+ *
+ * that is required, trapped and emulated by the Linux kernel. However, all
+ * RDHWR encodings yield address error exceptions on the TX79 since the SQ
+ * offset is odd. Therefore all valid SQ instructions can execute normally.
+ * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
+ * between SQ and RDHWR, as the Linux kernel does.
+ */
+static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
+{
+ int base = extract32(ctx->opcode, 21, 5);
+ int rt = extract32(ctx->opcode, 16, 5);
+ int offset = extract32(ctx->opcode, 0, 16);
+
+#ifdef CONFIG_USER_ONLY
+ uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
+ uint32_t op2 = extract32(ctx->opcode, 6, 5);
+
+ if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
+ int rd = extract32(ctx->opcode, 11, 5);
+
+ gen_rdhwr(ctx, rt, rd, 0);
+ return;
+ }
+#endif
+
+ gen_tx79_sq(ctx, base, rt, offset);
+}
+
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@@ -25720,7 +25767,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
decode_opc_special2_legacy(env, ctx);
break;
case OPC_SPECIAL3:
- decode_opc_special3(env, ctx);
+ if (ctx->insn_flags & INSN_R5900) {
+ decode_tx79_sq(env, ctx); /* TX79_SQ */
+ } else {
+ decode_opc_special3(env, ctx);
+ }
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
--
2.7.4
- [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions, (continued)
- [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 14/34] target/mips: Placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 24/34] tests/tcg/mips: Test R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 26/34] tests/tcg/mips: Test R5900 three-operand MULTU1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 30/34] tests/tcg/mips: Test R5900 DIVU1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 29/34] tests/tcg/mips: Test R5900 DIV1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions, Aleksandar Markovic, 2018/10/22