[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 15/27] target/mips: Add emulation of MXU instruction
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 15/27] target/mips: Add emulation of MXU instruction S8LDD |
Date: |
Mon, 29 Oct 2018 16:20:06 +0100 |
From: Craig Janeczek <address@hidden>
Add support for emulating the S8LDD MXU instruction.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9d5bf7a..cb7a24b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24089,6 +24089,92 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
tcg_temp_free(t0);
}
+/*
+ * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF
+ */
+static void gen_mxu_s8ldd(DisasContext *ctx)
+{
+ TCGv t0, t1;
+ TCGLabel *l0;
+ uint32_t XRa, Rb, s8, optn3;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ l0 = gen_new_label();
+
+ XRa = extract32(ctx->opcode, 6, 4);
+ s8 = extract32(ctx->opcode, 10, 8);
+ optn3 = extract32(ctx->opcode, 18, 3);
+ Rb = extract32(ctx->opcode, 21, 5);
+
+ gen_load_mxu_cr(t0);
+ tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
+
+ gen_load_gpr(t0, Rb);
+ tcg_gen_addi_tl(t0, t0, (int8_t)s8);
+
+ switch (optn3) {
+ /* XRa[7:0] = tmp8 */
+ case MXU_OPTN3_PTN0:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ gen_load_mxu_gpr(t0, XRa);
+ tcg_gen_deposit_tl(t0, t0, t1, 0, 8);
+ break;
+ /* XRa[15:8] = tmp8 */
+ case MXU_OPTN3_PTN1:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ gen_load_mxu_gpr(t0, XRa);
+ tcg_gen_deposit_tl(t0, t0, t1, 8, 8);
+ break;
+ /* XRa[23:16] = tmp8 */
+ case MXU_OPTN3_PTN2:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ gen_load_mxu_gpr(t0, XRa);
+ tcg_gen_deposit_tl(t0, t0, t1, 16, 8);
+ break;
+ /* XRa[31:24] = tmp8 */
+ case MXU_OPTN3_PTN3:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ gen_load_mxu_gpr(t0, XRa);
+ tcg_gen_deposit_tl(t0, t0, t1, 24, 8);
+ break;
+ /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
+ case MXU_OPTN3_PTN4:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
+ break;
+ /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
+ case MXU_OPTN3_PTN5:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_shli_tl(t1, t1, 8);
+ tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
+ break;
+ /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
+ case MXU_OPTN3_PTN6:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);
+ tcg_gen_mov_tl(t0, t1);
+ tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);
+ tcg_gen_shli_tl(t1, t1, 16);
+ tcg_gen_or_tl(t0, t0, t1);
+ break;
+ /* XRa = {tmp8, tmp8, tmp8, tmp8} */
+ case MXU_OPTN3_PTN7:
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_deposit_tl(t1, t1, t1, 8, 8);
+ tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
+ break;
+ }
+
+ gen_store_mxu_gpr(t0, XRa);
+
+ gen_set_label(l0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
/*
* Decoding engine for MXU
@@ -25134,9 +25220,7 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_MXU_S8LDD:
- /* TODO: Implement emulation of S8LDD instruction. */
- MIPS_INVAL("OPC_MXU_S8LDD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_mxu_s8ldd(ctx);
break;
case OPC_MXU_S8STD:
/* TODO: Implement emulation of S8STD instruction. */
--
2.7.4
- [Qemu-devel] [PULL 01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases, (continued)
- [Qemu-devel] [PULL 01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 09/27] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 07/27] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 05/27] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 06/27] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 10/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 25/27] linux-user: Read and set FP ABI value from MIPS abiflags, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 16/27] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 11/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 15/27] target/mips: Add emulation of MXU instruction S8LDD,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 26/27] linux-user: Determine the desired FPU mode from MIPS.abiflags, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 24/27] linux-user: Extract MIPS abiflags from ELF file, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 18/27] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 14/27] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 17/27] target/mips: Add emulation of MXU instruction D16MAC, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 13/27] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 04/27] target/mips: Amend MXU instruction opcodes, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 20/27] target/mips: Move MXU_EN check one level higher, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 21/27] target/mips: Amend MXU ASE overview note, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 19/27] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/29